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公开(公告)号:US08362626B2
公开(公告)日:2013-01-29
申请号:US12197938
申请日:2008-08-25
申请人: Nobuya Koike , Shinya Nagata
发明人: Nobuya Koike , Shinya Nagata
IPC分类号: H01L23/34
CPC分类号: H01L23/49575 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要: An SiP (semiconductor device) using a stacked packaging method for stacking a microcomputer IC chip over a driver IC chip in which circuits sensitive to heat or noise, including an analog to digital conversion circuit, a digital to analog conversion circuit, a sense amplifier circuit of a memory (RAM or ROM), or a power supply circuit of a microcomputer IC chip, are prevented from two-dimensionally overlapping with a driver circuit of the lower-side driver IC chip to reduce, during the operation, the effect of heat or noise, which the circuits sensitive to heat or noise of the microcomputer IC chip receive from the driver circuit of the lower-side driver IC chip, thereby improving the operation stability of the SiP (semiconductor device) using the stacked packaging method.
摘要翻译: 一种使用堆叠封装方法的SiP(半导体器件),用于在包括模数转换电路,数模转换电路,读/放大器电路的热或噪声敏感电路的驱动器IC芯片上堆叠微计算机IC芯片 的存储器(RAM或ROM)或微计算机IC芯片的电源电路被防止与下侧驱动器IC芯片的驱动电路二维重叠,以在操作期间减少热量的影响 或噪声,微电脑IC芯片的热或噪声敏感的电路从下侧驱动器IC芯片的驱动电路接收,从而通过堆叠封装方法提高SiP(半导体器件)的操作稳定性。
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公开(公告)号:US08338927B2
公开(公告)日:2012-12-25
申请号:US13225788
申请日:2011-09-06
IPC分类号: H01L21/44
CPC分类号: H01L21/4835 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/45144 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/0106 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H05K3/3426 , H05K2201/10795 , H05K2201/10909 , Y02P70/613 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要: The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.
摘要翻译: 半导体器件包括半导体芯片,芯片安装部分,悬挂引线和多个引线。 多个引线中的每一个具有第一部分和第二部分,并且悬架引线具有第一部分和第二部分。 多个引线中的每一个的第一部分和悬挂引线分别从密封体的多个侧表面伸出。 多个引线的侧面部分和悬挂引线分别从密封体的多个侧面露出。 在俯视图中,悬架引线的第一部分的正面的面积大于多根引线中的每一个的第一部分的正面的面积。
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公开(公告)号:US20120261825A1
公开(公告)日:2012-10-18
申请号:US13533391
申请日:2012-06-26
申请人: Nobuya KOIKE , Atsushi Fujiki , Norio Kido , Yukihiro Sato , Hiroyuki Nakamura
发明人: Nobuya KOIKE , Atsushi Fujiki , Norio Kido , Yukihiro Sato , Hiroyuki Nakamura
IPC分类号: H01L23/48
CPC分类号: H01L21/565 , H01L23/49503 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L2224/04042 , H01L2224/29111 , H01L2224/29139 , H01L2224/32245 , H01L2224/32257 , H01L2224/40095 , H01L2224/40245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48463 , H01L2224/4847 , H01L2224/49171 , H01L2224/49175 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device.A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.
摘要翻译: 通过改变半导体器件的结构,安装时的安装布线的布局变得有效。 第一芯片安装在第一芯片焊盘上,第二芯片也安装在第二芯片焊盘上。 第一管芯焊盘和第二管芯焊盘与密封体40的第一侧面和第二侧平行地进行分割结构。结果,用于从第一芯片输出的引脚和用于控制驱动电路的引脚 可以使其能够从反方向投影,并可以将安装时的布线布局设置为最小路线。
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公开(公告)号:US20090215230A1
公开(公告)日:2009-08-27
申请号:US12358387
申请日:2009-01-23
申请人: Akira MUTO , Nobuya Koike , Katsuo Arai , Atsushi Fujiki
发明人: Akira MUTO , Nobuya Koike , Katsuo Arai , Atsushi Fujiki
IPC分类号: H01L21/56
CPC分类号: H01L21/565 , H01L23/3107 , H01L23/433 , H01L23/4334 , H01L23/49537 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/33 , H01L24/36 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/83 , H01L25/115 , H01L25/117 , H01L2224/26145 , H01L2224/26175 , H01L2224/27013 , H01L2224/29101 , H01L2224/2929 , H01L2224/29339 , H01L2224/29499 , H01L2224/32014 , H01L2224/32245 , H01L2224/33181 , H01L2224/40247 , H01L2224/4899 , H01L2224/73263 , H01L2224/83051 , H01L2224/83101 , H01L2224/83139 , H01L2224/83192 , H01L2224/83801 , H01L2224/83815 , H01L2224/8385 , H01L2224/83855 , H01L2224/83862 , H01L2224/83885 , H01L2224/84801 , H01L2224/8485 , H01L2225/1029 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01067 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/00 , H01L2924/07025 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099 , H01L2224/37599
摘要: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip. At the same time, paste-like bonding material and a film member are placed between the source terminal 3 and gate terminal and the semiconductor chip. The paste-like bonding material is cured and turned into bonding material. As the result of use of the film members, variation in the thickness of the bonding material is suppressed.
摘要翻译: 提高树脂密封半导体封装的放射性能,进一步提高其制造成品率。 耦合到半导体芯片的背表面漏电极的漏极端子在封装树脂部分的背面露出。 以下部分和端子的一部分暴露在封装树脂部分的顶表面处:耦合到半导体芯片的源极焊盘电极的源极端子的第一部分和耦合到半导体芯片的栅极焊盘电极的栅极端子 。 源极端子和栅极端子的第二部分的剩余部分在封装树脂部分的背面露出。 当制造该半导体器件时,将接合材料和膜构件放置在漏极端子和半导体芯片之间。 同时,在源极端子3和栅极端子与半导体芯片之间放置糊状结合材料和膜部件。 糊状接合材料固化并变成粘结材料。 作为使用膜构件的结果,抑制了接合材料的厚度的变化。
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公开(公告)号:US20090068796A1
公开(公告)日:2009-03-12
申请号:US12267079
申请日:2008-11-07
IPC分类号: H01L21/50
CPC分类号: H01L23/49524 , H01L23/4952 , H01L24/03 , H01L24/05 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/84 , H01L24/91 , H01L29/7816 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/37147 , H01L2224/40245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/73221 , H01L2224/84801 , H01L2224/8485 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2924/00015 , H01L2924/207
摘要: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.
摘要翻译: 需要提供一种能够降低将功率晶体管和控制集成电路集成到单个半导体芯片的半导体器件中的功率晶体管的导通电阻的技术。 另外需要提供能够减少半导体器件的芯片尺寸的技术。 半导体芯片包括形成功率晶体管的功率晶体管形成区域,形成逻辑电路的逻辑电路形成区域和形成模拟电路的模拟电路形成区域。 在功率晶体管形成区域中形成焊盘。 焊盘和引线通过横截面大于导线的夹子连接。 另一方面,焊盘通过导线29连接。
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公开(公告)号:US06320270B1
公开(公告)日:2001-11-20
申请号:US09500536
申请日:2000-02-09
申请人: Kuniharu Muto , Atsushi Nishikizawa , Jyunichi Tsuchiya , Toshiyuki Hata , Nobuya Koike , Ichio Shimizu
发明人: Kuniharu Muto , Atsushi Nishikizawa , Jyunichi Tsuchiya , Toshiyuki Hata , Nobuya Koike , Ichio Shimizu
IPC分类号: H01L23495
CPC分类号: H01L23/4334 , H01L21/565 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/05639 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat- radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.
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公开(公告)号:US5956231A
公开(公告)日:1999-09-21
申请号:US539075
申请日:1995-10-04
申请人: Kazuji Yamada , Akira Tanaka , Ryuichi Saito , Yasutoshi Kurihara , Tadao Kushima , Takashi Haramaki , Yoshihiko Koike , Takashi Hosokawa , Mamoru Sawahata , Masahiro Koizumi , Jin Onuki , Kazuhiro Suzuki , Isao Kobayashi , Hideo Shimizu , Yutaka Higashimura , Shigeki Sekine , Nobuya Koike , Hideya Kokubun
发明人: Kazuji Yamada , Akira Tanaka , Ryuichi Saito , Yasutoshi Kurihara , Tadao Kushima , Takashi Haramaki , Yoshihiko Koike , Takashi Hosokawa , Mamoru Sawahata , Masahiro Koizumi , Jin Onuki , Kazuhiro Suzuki , Isao Kobayashi , Hideo Shimizu , Yutaka Higashimura , Shigeki Sekine , Nobuya Koike , Hideya Kokubun
IPC分类号: H01L23/049 , H01L23/495 , H01L25/065 , H02M7/00 , H05K7/02 , H05K7/04
CPC分类号: H01L23/49562 , H01L23/049 , H01L24/49 , H01L25/0655 , H01L25/072 , H01L25/18 , H02M7/003 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/4943 , H01L2224/49431 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01041 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351
摘要: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.
摘要翻译: 一种半导体器件,其中多个半导体元件被结合到绝缘体衬底上的至少一个电极图案上,所述绝缘体衬底在主表面上形成多个电极图案,所述半导体元件的每个电极电连接到所述电极图案, 绝缘体基板的另一表面被结合到散热基底上,散热基座的上表面覆盖有用于从外部环境切断半导体元件的构件,将绝缘体基板上的电极与电极电连接的端子 设置在切断部件外侧,散热基体的材料的线膨胀系数大于半导体元件的线膨胀系数,小于半导体元件的线膨胀系数的3倍,导热系数 大于100 W / mK,半音 电感元件布置在至少一个电极表面上,并且在至少两个区域中被绝缘体基底上的另一个电极表面分隔。
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公开(公告)号:US08994159B2
公开(公告)日:2015-03-31
申请号:US13740354
申请日:2013-01-14
申请人: Hiroyuki Nakamura , Akira Muto , Nobuya Koike , Atsushi Nishikizawa , Yukihiro Sato , Katsuhiko Funatsu
发明人: Hiroyuki Nakamura , Akira Muto , Nobuya Koike , Atsushi Nishikizawa , Yukihiro Sato , Katsuhiko Funatsu
IPC分类号: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号: H01L23/495 , H01L21/4828 , H01L21/56 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/2919 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/49171 , H01L2224/73265 , H01L2224/838 , H01L2224/85439 , H01L2224/85455 , H01L2224/92247 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2924/3512 , H01L2224/05599
摘要: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.
摘要翻译: 为了防止在树脂密封型半导体封装中产生用于安装半导体芯片的芯片接合材料中的裂纹。 半导体芯片通过芯片接合材料安装在芯片焊盘的上表面上,然后用绝缘树脂密封。 要与绝缘树脂接触的芯片焊盘的顶表面被粗糙化,而芯片焊盘的底表面和外部引线部分没有被表面粗糙化。
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公开(公告)号:US20130127032A1
公开(公告)日:2013-05-23
申请号:US13740354
申请日:2013-01-14
申请人: Hiroyuki NAKAMURA , Akira MUTO , Nobuya KOIKE , Atsushi NISHIKIZAWA , Yukihiro SATO , Katsuhiko FUNATSU
发明人: Hiroyuki NAKAMURA , Akira MUTO , Nobuya KOIKE , Atsushi NISHIKIZAWA , Yukihiro SATO , Katsuhiko FUNATSU
IPC分类号: H01L23/495 , H01L21/56
CPC分类号: H01L23/495 , H01L21/4828 , H01L21/56 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/2919 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/49171 , H01L2224/73265 , H01L2224/838 , H01L2224/85439 , H01L2224/85455 , H01L2224/92247 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2924/3512 , H01L2224/05599
摘要: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.
摘要翻译: 为了防止在树脂密封型半导体封装中产生用于安装半导体芯片的芯片接合材料中的裂纹。 半导体芯片通过芯片接合材料安装在芯片焊盘的上表面上,然后用绝缘树脂密封。 要与绝缘树脂接触的芯片焊盘的顶表面被粗糙化,而芯片焊盘的底表面和外部引线部分没有被表面粗糙化。
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公开(公告)号:US08299599B2
公开(公告)日:2012-10-30
申请号:US13040234
申请日:2011-03-03
申请人: Hiroyuki Nakamura , Atsushi Fujiki , Tatsuhiro Seki , Nobuya Koike , Yukihiro Sato , Kisho Ashida
发明人: Hiroyuki Nakamura , Atsushi Fujiki , Tatsuhiro Seki , Nobuya Koike , Yukihiro Sato , Kisho Ashida
CPC分类号: H01L27/07 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/66 , H01L2224/02166 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/37599 , H01L2224/40095 , H01L2224/40247 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/49175 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01015 , H01L2924/01047 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.
摘要翻译: 提高半导体器件的性能和可靠性。 对于半导体芯片CP1,用于开关的功率MOSFET Q1和Q2,用于检测功率MOSFET Q1的发热的二极管DD1,用于检测功率MOSFET Q2的发热的二极管DD2和多个焊盘电极PD 。 功率MOSFET Q1和二极管DD1布置在侧面SD1侧的第一MOSFET区域RG1中,功率MOSFET Q2和二极管DD2布置在侧面SD2侧的第二MOSFET区RG2中。 二极管DD1沿着侧面SD1配置,二极管DD2沿着侧面SD2配置,除了用于源极的焊盘电极PDS1和PDS2以外的所有焊盘电极PD沿着二极管DD1和DD2之间的侧面SD3排列。
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