利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.013 秒)

    METHOD OF FORMING TUNGSTEN POLYMETAL GATE HAVING LOW RESISTANCE
    2.
    发明申请
    METHOD OF FORMING TUNGSTEN POLYMETAL GATE HAVING LOW RESISTANCE 失效
    形成具有低电阻性的钨金属聚合物的方法

    公开(公告)号：US20080081452A1

    公开(公告)日：2008-04-03

    申请号：US11693137

    申请日：2007-03-29

    申请人： Soo Hyun KIM ,  Noh Jung KWAK ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Kwan Yong LIM

    发明人： Soo Hyun KIM ,  Noh Jung KWAK ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Kwan Yong LIM

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28061 ,  H01L29/4941

    摘要： A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.

    摘要翻译： 通过在半导体衬底上形成栅极绝缘层和多晶硅层来制造钨多金属栅极; 在所述多晶硅层上沉积阻挡层; 通过ALD工艺在阻挡层上沉积钨成核层; 通过CVD工艺在钨成核层上沉积钨层; 在钨层上沉积硬掩模层; 并且蚀刻硬掩模层，钨层，钨成核层，势垒层，多晶硅层和栅极绝缘层。

    Method for fabricating semiconductor device
    3.
    发明授权
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US08314030B2

    公开(公告)日：2012-11-20

    申请号：US12489747

    申请日：2009-06-23

    申请人： Jum-Yong Park ,  Noh-Jung Kwak ,  Yong-Soo Choi ,  Cheol-Hwi Ryu

    发明人： Jum-Yong Park ,  Noh-Jung Kwak ,  Yong-Soo Choi ,  Cheol-Hwi Ryu

    IPC分类号： H01L21/302 ,  B44C1/22

    CPC分类号： C09G1/02 ,  B24B37/044

    摘要： A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.

    摘要翻译： 提供了一种通过化学机械抛光（CMP）工艺制造半导体器件的方法。 CMP工艺通过使用浆料进行。 半导体器件制造方法可以通过使用相对于目标表面具有高抛光选择性的CMP浆料，抗划痕特性和高全局平坦化特性进行CMP工艺来确保器件的可靠性和经济效率。

    METHOD FOR FORMING COPPER WIRING IN A SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR FORMING COPPER WIRING IN A SEMICONDUCTOR DEVICE 失效
    在半导体器件中形成铜线的方法

    公开(公告)号：US20100210104A1

    公开(公告)日：2010-08-19

    申请号：US12427870

    申请日：2009-04-22

    申请人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

    发明人： Hyung Soon Park ,  Noh Jung Kwak ,  Seung Jin Yeom ,  Choon Kun Ryu ,  Jong Goo Jung ,  Sung Jun Kim

    IPC分类号： H01L21/768 ,  H01L21/306

    CPC分类号： H01L21/02074 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76883

    摘要： A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

    摘要翻译： 本文公开了一种用于形成铜布线的方法和防止半导体器件中的铜离子迁移。 该方法包括对经过CMP工艺形成铜线的铜层进行后清洗处理。 后清洗过程包括使用基于柠檬酸的化学品进行初级化学清洗。 然后在使用抗坏血酸的化学品进行了主要化学清洗的铜层上进行二次化学清洗。 在完成后清洗处理之后，防止了铜离子随时间的迁移，从而提高了半导体器件的可靠性。

    Method of forming a contact hole of a semiconductor device
    5.
    发明授权
    Method of forming a contact hole of a semiconductor device 失效
    形成半导体器件的接触孔的方法

    公开(公告)号：US5940730A

    公开(公告)日：1999-08-17

    申请号：US771579

    申请日：1996-12-20

    申请人： Noh Jung Kwak ,  Choon Hwan Kim

    发明人： Noh Jung Kwak ,  Choon Hwan Kim

    IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/461

    CPC分类号： H01L21/76804

    摘要： The present invention relates to a method of forming a contact hole of a semiconductor device, and discloses a method of forming a contact hole of a semiconductor device which can remove an oxide film formed on the bottom of the contact hole, and make the edge portions of the entrance to the contact hole and reduce the topology of the contact hole by performing high frequency plasma etching processes in two stage in which the condition of pressure and electric power are different.

    摘要翻译： 本发明涉及一种形成半导体器件的接触孔的方法，并且公开了一种形成半导体器件的接触孔的方法，该半导体器件可以去除形成在接触孔的底部上的氧化物膜，并使边缘部分 的接触孔的入口，并且通过在压力和电力的条件不同的两个阶段中进行高频等离子体蚀刻工艺来减小接触孔的拓扑。

    Method for fabricating semiconductor device with buried gates
    7.
    发明授权
    Method for fabricating semiconductor device with buried gates 有权
    制造具有埋栅的半导体器件的方法

    公开(公告)号：US08598012B2

    公开(公告)日：2013-12-03

    申请号：US12832137

    申请日：2010-07-08

    申请人： Jong-Han Shin ,  Noh-Jung Kwak ,  Myung-Ok Kim

    发明人： Jong-Han Shin ,  Noh-Jung Kwak ,  Myung-Ok Kim

    IPC分类号： H01L21/76 ,  H01L21/3205

    CPC分类号： H01L21/76229 ,  H01L21/76897 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.

    摘要翻译： 一种用于制造半导体器件的方法包括在衬底上顺序堆叠衬垫氧化物层和硬掩模层，在衬底上形成器件隔离层，形成覆盖衬底图案，其构造成打开衬底的第一区域并覆盖第二 区域，去除硬掩模层，去除覆盖层图案，以及去除焊盘氧化物层。

    Method of forming tungsten polymetal gate having low resistance
    9.
    发明授权
    Method of forming tungsten polymetal gate having low resistance 失效
    具有低电阻的钨多金属门形成方法

    公开(公告)号：US07541269B2

    公开(公告)日：2009-06-02

    申请号：US11693137

    申请日：2007-03-29

    申请人： Soo Hyun Kim ,  Noh Jung Kwak ,  Baek Mann Kim ,  Young Jin Lee ,  Sun Woo Hwang ,  Kwan Yong Lim

    发明人： Soo Hyun Kim ,  Noh Jung Kwak ,  Baek Mann Kim ,  Young Jin Lee ,  Sun Woo Hwang ,  Kwan Yong Lim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28061 ,  H01L29/4941

    摘要： A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.

    摘要翻译： 通过在半导体衬底上形成栅极绝缘层和多晶硅层来制造钨多金属栅极; 在所述多晶硅层上沉积阻挡层; 通过ALD工艺在阻挡层上沉积钨成核层; 通过CVD工艺在钨成核层上沉积钨层; 在钨层上沉积硬掩模层; 并且蚀刻硬掩模层，钨层，钨成核层，势垒层，多晶硅层和栅极绝缘层。