System and method for maintaining memory page sharing in a virtual environment
    1.
    发明授权
    System and method for maintaining memory page sharing in a virtual environment 有权
    在虚拟环境中维护内存页共享的系统和方法

    公开(公告)号:US08006043B2

    公开(公告)日:2011-08-23

    申请号:US12246402

    申请日:2008-10-06

    申请人: Ole Agesen

    发明人: Ole Agesen

    IPC分类号: G06F12/08

    摘要: In a virtualized system using memory page sharing, a method is provided for maintaining sharing when Guest code attempts to write to the shared memory. In one embodiment, virtualization logic uses a pattern matcher to recognize and intercept page zeroing code in the Guest OS. When the page zeroing code is about to run against a page that is already zeroed, i.e., contains all zeros, and is being shared, the memory writes in the page zeroing code have no effect. The virtualization logic skips over the writes, providing an appearance that the Guest OS page zeroing code has run to completion but without performing any of the writes that would have caused a loss of page sharing. The pattern matcher can be part of a binary translator that inspects code before it executes.

    摘要翻译: 在使用内存页面共享的虚拟化系统中,提供了一种方法,用于在访客代码尝试写入共享内存时保持共享。 在一个实施例中,虚拟化逻辑使用模式匹配器来识别和拦截访客操作系统中的页面归零代码。 当页面归零代码即将针对已经归零的页面运行时,即包含全部零,并且正在共享时,页面调零代码中的内存写入不起作用。 虚拟化逻辑跳过写入,提供Guest OS页面调零代码已经运行到完成的外观,但不执行会导致页面共享丢失的任何写入。 模式匹配器可以是在执行代码之前检查代码的二进制转换器的一部分。

    Prediction Mechanism for Subroutine Returns in Binary Translation Sub-Systems of Computers
    2.
    发明申请
    Prediction Mechanism for Subroutine Returns in Binary Translation Sub-Systems of Computers 审中-公开
    计算机二进制翻译子系统中子程序返回的预测机制

    公开(公告)号:US20090254709A1

    公开(公告)日:2009-10-08

    申请号:US12485679

    申请日:2009-06-16

    申请人: Ole AGESEN

    发明人: Ole AGESEN

    IPC分类号: G06F9/54 G06F12/08

    CPC分类号: G06F8/52

    摘要: A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the return address after any IL call to a subroutine at a target entry address P, the corresponding OL return address is stored in an array at a location determined by an index calculated as a function of P. After completion of execution of the OL translation of the IL subroutine, execution is transferred to the address stored in the array at the location where the OL return address was previously stored. A confirm instruction block is included in each OL call site to determine whether the transfer was to the correct or incorrect call site, and a back-up routine is included to handle the cases of incorrect call sites.

    摘要翻译: 访客系统的输入语言(IL)指令的序列例如通过二进制转换被转换成执行OL指令的主机系统的输出语言(OL)指令的相应序列。 为了在目标入口地址P处的子程序的任何IL调用之后确定返回地址,相应的OL返回地址被存储在由作为P的函数计算的索引确定的位置的阵列中。在完成执行 IL子程序的OL转换,执行被传送到在先前存储OL返回地址的位置存储在数组中的地址。 每个OL呼叫站点中都包含确认指令块,以确定传输是否为正确或不正确的呼叫站点,还包括备份程序来处理不正确的呼叫站点的情况。

    Restricting memory access to protect data when sharing a common address space

    公开(公告)号:US07487313B1

    公开(公告)日:2009-02-03

    申请号:US11865635

    申请日:2007-10-01

    IPC分类号: G06F12/00

    摘要: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

    Restricting memory access to protect data when sharing a common address space
    4.
    发明授权
    Restricting memory access to protect data when sharing a common address space 有权
    限制内存访问以在共享公共地址空间时保护数据

    公开(公告)号:US07277998B1

    公开(公告)日:2007-10-02

    申请号:US10917732

    申请日:2004-08-12

    IPC分类号: G06F12/00

    摘要: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

    摘要翻译: 第一软件实体占用第二软件实体的线性地址空间的一部分,并且防止第二软件实体访问第一软件实体的存储器。 例如,在本发明的一个实施例中,第一软件实体是支持虚拟机(VM)的第二软件实体的虚拟机监视器(VMM)。 VMM有时直接从VM执行访客指令,而在其他时候,VMM执行从访客指令导出的二进制翻译指令。 当执行二进制转换指令时,VMM使用存储器分段来保护其内存。 当直接执行访客指令时,VMM可以使用存储器分段或存储器寻呼机制来保护其存储器。 当存储器分页机制在直接执行期间有效时,可以选择性地停止对存储器分段机制的保护,以提高虚拟计算机系统的效率。

    Method and system for performing virtual to physical address translations in a virtual machine monitor
    5.
    发明授权
    Method and system for performing virtual to physical address translations in a virtual machine monitor 有权
    用于在虚拟机监视器中执行虚拟到物理地址转换的方法和系统

    公开(公告)号:US07069413B1

    公开(公告)日:2006-06-27

    申请号:US10354556

    申请日:2003-01-29

    IPC分类号: G06F12/00

    摘要: The invention is used in a virtual machine monitor for a multiprocessing system that includes a virtual memory system. During a software-based processing of a guest instruction, including translating or interpreting a guest instruction, mappings between virtual addresses and physical addresses are retained in memory until processing of the guest instruction is completed. The retained mappings may be cleared after each guest instruction has been processed, or after multiple guest instructions have been processed. Information may also be stored to indicate that an attempt to map a virtual address to a physical address was not successful. The invention may be extended beyond virtual machine monitors to other systems involving the software-based processing of instructions, and beyond multiprocessing systems to other systems involving concurrent access to virtual memory management data.

    摘要翻译: 本发明用于包括虚拟存储器系统的多处理系统的虚拟机监视器中。 在访客指令的基于软件的处理中,包括翻译或解释访客指令,虚拟地址和物理地址之间的映射被保留在存储器中,直到访客指令的处理完成。 保留的映射可以在每个客户指令被处理之后或在多个客户指令被处理之后被清除。 还可以存储信息以指示将虚拟地址映射到物理地址的尝试不成功。 本发明可以扩展到虚拟机监视器以外的其他系统,涉及指令的基于软件的处理,并且超出多处理系统到涉及对虚拟存储器管理数据的并发访问的其他系统。

    Method and system for implementing subroutine calls and returns in binary translation sub-systems of computers
    6.
    发明授权
    Method and system for implementing subroutine calls and returns in binary translation sub-systems of computers 有权
    用于在计算机的二进制翻译子系统中实现子程序调用和返回的方法和系统

    公开(公告)号:US06711672B1

    公开(公告)日:2004-03-23

    申请号:US09668091

    申请日:2000-09-22

    申请人: Ole Agesen

    发明人: Ole Agesen

    IPC分类号: G06F9455

    摘要: A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the correct return address after any IL call to a subroutine, the corresponding OL return address is stored in an array at a location determined by a hash function. After completion of execution of the OL translation of the IL subroutine, execution is transferred to the address stored in the array at the location where the correct OL return address was previously stored. This location may have been overwritten by some other OL return address. This transfer will therefore be to one of three places: 1) either back to the correct OL call site, in which case execution may continue as normal; 2) directly to a back-up return address recovery module; or 3) to an incorrect OL call site (created upon translation of some other IL subroutine call), in which case execution is transferred to the back-up recovery module. A confirmation instruction block is included in each OL call site to determine whether the transfer was to the correct or incorrect call site.

    摘要翻译: 访客系统的输入语言(IL)指令的序列例如通过二进制转换被转换成执行OL指令的主机系统的输出语言(OL)指令的相应序列。 为了在任何IL调用子程序后确定正确的返回地址,相应的OL返回地址存储在由散列函数确定的位置的数组中。 在执行IL子程序的OL转换完成后,执行将被转移到阵列中存储了正确OL返回地址的位置的地址。 该位置可能已被其他一些OL返回地址覆盖。 因此,这种转移将是三个地方之一:1)返回正确的OL呼叫站点,在这种情况下执行可能正常; 2)直接到备份返回地址恢复模块; 或3)到不正确的OL调用站点(在其他IL子程序调用的转换时创建),在这种情况下,执行将传输到备份恢复模块。 每个OL呼叫站点中都包含确认指令块,以确定传输是否是正确或不正确的呼叫站点。

    Method and apparatus for encoding and decoding delta encoded information
to locate live pointers in program data stacks
    7.
    发明授权
    Method and apparatus for encoding and decoding delta encoded information to locate live pointers in program data stacks 失效
    用于编码和解码增量编码信息以在程序数据堆栈中定位实时指针的方法和装置

    公开(公告)号:US5909579A

    公开(公告)日:1999-06-01

    申请号:US847770

    申请日:1997-04-23

    IPC分类号: G06F12/02 H03M3/02 G06B9/44

    摘要: Live pointer information for a stream of bytecodes is precomputed for each bytecode. The precomputed full live pointer information is stored only for bytecodes at predetermined intervals in the stream. Between the bytecodes for which full live pointer information is stored, changes in the live pointer information produced by each bytecode are encoded using a suitable compressive coding and stored. Later, when a program which needs the live pointer information, such as garbage collection, is initiated, the full live pointer information for the nearest bytecode preceding the desired bytecode boundary is retrieved along with the intervening coded changes. The changes are decoded and applied to the retrieved live pointer information to generate the live pointer information at the desired bytecode boundary. In one embodiment of the invention, the live pointer changes are delta encoded so that each code contains information relating to the live pointer changes produced by a bytecode from the live pointer information as modified by the previous delta code. In another embodiment of the invention, the delta coded changes are encoded with a Huffman encoding scheme.

    摘要翻译: 每个字节码预先计算字节码流的实时指针信息。 预计算的完整实况指针信息仅在流中以预定间隔存储在字节码中。 在存储完整的实时指针信息的字节码之间,使用适当的压缩编码对每个字节码产生的实况指针信息进行改变并进行存储。 之后,当开始需要诸如垃圾收集之类的活动指针信息的程序时,将检索所需字节码边界之前的最近字节码的完整实况指针信息以及中间编码的变化。 这些改变被解码并应用于检索到的实时指针信息以在期望的字节码边界处生成实时指针信息。 在本发明的一个实施例中,实时指针变化被增量编码,使得每个代码包含与由先前的增量代码修改的来自实时指针信息的字节码产生的实况指针变化相关的信息。 在本发明的另一个实施例中,Δ编码改变用霍夫曼编码方案编码。

    Bounded-pause time garbage collection system and method including write
barrier associated with a source instance of a partially relocated
object
    8.
    发明授权
    Bounded-pause time garbage collection system and method including write barrier associated with a source instance of a partially relocated object 失效
    有界 - 暂停时间垃圾收集系统和方法,包括与部分重定位对象的源实例相关联的写入障碍

    公开(公告)号:US5873105A

    公开(公告)日:1999-02-16

    申请号:US883291

    申请日:1997-06-26

    CPC分类号: G06F12/0276 Y10S707/99957

    摘要: A write barrier to stores into a partially relocated large or popular memory object facilitates bounded pause time implementations of relocating garbage collectors, including e.g., copying collectors, generational collectors, and collectors providing compaction. Such a write barrier allows a garbage collector implementation to interrupt relocation of large or popular memory objects so as to meet bounded pause time guarantees. A partially relocated object identifier store including "copy from" identifier storage accessible to write barrier logic allows the write barrier logic to maintain consistency between FromSpace and ToSpace instances of a partially relocated memory object. "Copy from" identifier storage allows the write barrier logic, or a trap handler responsive thereto, to broadcast a store-oriented memory access targeting the FromSpace instance to both FromSpace and ToSpace instances. Optional "How far" indication storage facilitates differentiation by the write barrier logic between a copied portion and an uncopied portion of the partially relocated memory object.

    摘要翻译: 将存储到部分重定位的大型或流行的存储器对象中的写入屏障有助于重新定位垃圾收集器的有限暂停时间实现,包括例如复制收集器,代人收集器和提供压缩的收集器。 这样的写屏障允许垃圾回收器实现中断大型或流行的存储器对象的重新定位,以便满足有限的暂停时间保证。 包含写入屏障逻辑可访问的“复制”标识符存储的部分重新定位的对象标识符存储允许写入屏障逻辑保持部分重新定位的存储器对象的FromSpace和ToSpace实例之间的一致性。 从“标识符存储器复制”允许写屏障逻辑或响应于此的陷阱处理器将针对FromSpace实例的面向存储器的存储器访问广播到FromSpace和ToSpace实例。 可选的“多远”指示存储有助于通过写入屏障逻辑在部分重定位的存储器对象的复制部分和未遮盖部分之间进行区分。

    System and method for avoiding synchronization bugs through virtualization
    9.
    发明授权
    System and method for avoiding synchronization bugs through virtualization 有权
    通过虚拟化避免同步错误的系统和方法

    公开(公告)号:US08572606B1

    公开(公告)日:2013-10-29

    申请号:US11365012

    申请日:2006-03-01

    IPC分类号: G06F9/455

    摘要: A system and method for reducing the likelihood of concurrency errors by identifying vulnerable segments of computer code and stalling other virtual machine threads of execution. According to one embodiment of the present invention, the vulnerable segment is identified at runtime, for example in a dynamic translator. According to another embodiment of the present invention, the vulnerable segment is identified ahead of time, for example in a static translator. According to yet another embodiment of the present invention, the vulnerable segment is identified in the binary translator of a virtual machine monitor.

    摘要翻译: 通过识别计算机代码的易受攻击的部分并拖延执行其他虚拟机线程来减少并发错误的可能性的系统和方法。 根据本发明的一个实施例,在运行时识别易受攻击的段,例如在动态翻译器中。 根据本发明的另一个实施例,提前识别易受攻击的段,例如在静态转换器中。 根据本发明的另一个实施例,在虚拟机监视器的二进制转换器中识别易受攻击的段。

    Optimizing segment access in binary translation
    10.
    发明授权
    Optimizing segment access in binary translation 有权
    优化二进制翻译中的段访问

    公开(公告)号:US08316193B2

    公开(公告)日:2012-11-20

    申请号:US12629682

    申请日:2009-12-02

    IPC分类号: G06F12/00

    摘要: A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a number of steps in the code emitted by the binary translator.

    摘要翻译: 一种二进制转换器发出代码的机制,当段选择器被分配给段寄存器时,该代码将预先生成关于存储器段的信息。 二进制翻译器发出将在遇到使用该段寄存器的存储器访问时执行的代码,并且当评估存储器访问请求时,发出的代码将访问预生成的信息。 存储器访问(其中访问的字节数小于或等于预定值)通过二进制翻译器发出的代码中的多个步骤来验证。