公开(公告)号：US20180139401A1

公开(公告)日：2018-05-17

申请号：US15569083

申请日：2016-05-11

Applicant: PYXALIS

Inventor： Christian LIABEUF

IPC: H04N5/378 ,  H04N5/374 ,  H04N5/376

CPC classification number: H04N5/378 ,  H03M1/123 ,  H03M1/56 ,  H04N5/374 ,  H04N5/3745 ,  H04N5/376 ,  H04N5/3765

Abstract: A circuit for reading a pixel matrix array comprises, for each column of pixels of the matrix array: voltage-to-delay converting circuits receiving, on an input, a voltage value representative of the voltage of a read conductor of a respective column of pixels of the matrix array and delivering as output a binary signal called a comparative signal, this signal switched at a time dependent on the input voltage value; frequency-multiplying circuits, one for each of the voltage-to-delay converting circuits, receiving as input a primary clock signal and delivering as output secondary clock signals of multiplied frequency; and binary counters, receiving, on a first input, a the secondary clock signal, and, on a second input, a the binary comparative signal and counting at a rate dictated by the secondary clock signal until the binary comparative signal switches. An image sensor comprising a matrix array of pixels, in particular active pixels, and a read circuit is also provided.

公开(公告)号：US20160036427A1

公开(公告)日：2016-02-04

申请号：US14815292

申请日：2015-07-31

Applicant: PYXALIS

Inventor： Grégoire CHENEBAUX

IPC: H03K5/159

CPC classification number: H03K5/159 ,  G06F1/10 ,  G06F13/16 ,  H03K5/133

Abstract: Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays.

Abstract translation: 提供了通过几个相互相同的部分图案的光复制产生的大尺寸的集成电路，更准确地说，涉及从一个部分电路到随后的信号（特别是时钟信号）的传播延迟的补偿，而有关的信号必须到达各种部分电路 同时为整体正常运行。 在每个部分电路中提供的补偿电路包括用于主时钟信号的主传输线和具有多个输出的补偿线，以及用于选择一个输出的多路复用器，所选择的输出在各种局部电路中是不同的。 多路复用器在每个部分电路中提供本地时钟信号，尽管传播延迟，这些时钟信号是同步的。

公开(公告)号：US11800247B2

公开(公告)日：2023-10-24

申请号：US17719297

申请日：2022-04-12

Applicant: PYXALIS

Inventor： Marie Guillon

IPC: H04N25/46 ,  H04N25/53 ,  H04N25/75 ,  H04N25/771 ,  H04N25/778 ,  H01L27/146

CPC classification number: H04N25/46 ,  H04N25/53 ,  H04N25/75 ,  H04N25/771 ,  H04N25/778 ,  H01L27/1463

Abstract: A pixel matrix includes a sub-matrix of four adjacent pixels. Each of the pixels of the sub-matrix comprises: a set of a photoelectric-effect element and a memory point, a detection node, a transfer gate. The binning stage is connected to the set and is common with an adjacent pixel of the sub-matrix. At least one detection node per sub-matrix is common to two adjacent pixels of the sub-matrix. The pixel matrix furthermore comprises at least one readout stage per sub-matrix, connected to the common detection node.

公开(公告)号：US09781364B2

公开(公告)日：2017-10-03

申请号：US15216496

申请日：2016-07-21

Applicant: PYXALIS

Inventor： Grégoire Chenebaux

IPC: H04N5/363 ,  H04N5/355 ,  H04N5/374 ,  H04N5/378 ,  H01L27/146

CPC classification number: H04N5/363 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14643 ,  H04N5/35572 ,  H04N5/374 ,  H04N5/378

Abstract: An active pixel image sensor comprising a matrix of pixels organized in rows and columns and a read circuit comprising a distinct read pathway for each column of pixels, comprises: a photodiode, a storage node, a transfer transistor, a storage node reset transistor, a row select transistor and a transistor mounted as voltage follower; each read pathway comprises a subtraction block connected to receive, first, voltage at the terminals of the storage node of a pixel of the corresponding column and, second, a reference voltage of value substantially equal to the reset voltage of the pixels of the matrix seen at the input of the read pathway; the sensor comprises a controller for driving the transistors of pixels and the read circuit to perform an image acquisition in global shutter mode with subtraction of the reset noise and non-destructive reading of the pixels. A method for acquiring images is provided.

公开(公告)号：US20170077943A1

公开(公告)日：2017-03-16

申请号：US15309259

申请日：2015-05-04

Applicant: PYXALIS

Inventor： Laurent SAINT MARTIN ,  Grégoire CHENEBAUX

IPC: H03M1/56 ,  H04N5/378 ,  H04N5/357 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/56 ,  H03M1/00 ,  H03M1/0634 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/123 ,  H03M1/1245 ,  H04N5/3575 ,  H04N5/378

Abstract: Ramp analog-digital converters used in matrix image sensors to provide a digital value representative of a level of illumination of a pixel are provided. Two voltage samples are applied to a comparator, a counter is used to count pulses at a frequency F from a starting instant of the ramp until a toggling of the comparator. Two other voltage samples, one of which is added to a linear voltage ramp having an identical starting instant and slope to the first ramp, are applied to a second comparator, a half counting frequency F/2 is applied to the counter from the toggling of one of the comparators, and the content of the counter at the moment of toggling of the other comparator is stored. Two measurements of samples of the same signal or of two different signals are averaged without undergoing a digital conversion for each signal and a digital addition.

Abstract translation: 提供了在矩阵图像传感器中使用的用于提供表示像素的照明水平的数字值的斜坡模数转换器。 将两个电压样本施加到比较器，计数器用于从斜坡的起始时刻到比较器的切换来对频率F的脉冲进行计数。 将另外两个电压样本（其中之一加到具有相同起始时刻的线性电压斜坡和斜坡到第一斜坡的斜坡上）被施加到第二比较器，半计数频率F / 2从切换 存储比较器之一，并且存储在切换另一个比较器时计数器的内容。 对相同信号或两个不同信号的采样进行两次测量，而不对每个信号进行数字转换和数字加法。

公开(公告)号：US09923571B2

公开(公告)日：2018-03-20

申请号：US15309259

申请日：2015-05-04

Applicant: PYXALIS

Inventor： Laurent Saint Martin ,  Grégoire Chenebaux

IPC: H03M1/56 ,  H03M1/06 ,  H04N5/357 ,  H04N5/378 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/56 ,  H03M1/00 ,  H03M1/0634 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/123 ,  H03M1/1245 ,  H04N5/3575 ,  H04N5/378

Abstract: Ramp analog-digital converters used in matrix image sensors to provide a digital value representative of a level of illumination of a pixel are provided. Two voltage samples are applied to a comparator, a counter is used to count pulses at a frequency F from a starting instant of the ramp until a toggling of the comparator. Two other voltage samples, one of which is added to a linear voltage ramp having an identical starting instant and slope to the first ramp, are applied to a second comparator, a half counting frequency F/2 is applied to the counter from the toggling of one of the comparators, and the content of the counter at the moment of toggling of the other comparator is stored. Two measurements of samples of the same signal or of two different signals are averaged without undergoing a digital conversion for each signal and a digital addition.

公开(公告)号：US20170026595A1

公开(公告)日：2017-01-26

申请号：US15216496

申请日：2016-07-21

Applicant: PYXALIS

Inventor： Grégoire CHENEBAUX

IPC: H04N5/363 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/363 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14643 ,  H04N5/35572 ,  H04N5/374 ,  H04N5/378

Abstract: An active pixel image sensor comprising a matrix of pixels organized in rows and columns and a read circuit comprising a distinct read pathway for each column of pixels, comprises: a photodiode, a storage node, a transfer transistor, a storage node reset transistor, a row select transistor and a transistor mounted as voltage follower; each read pathway comprises a subtraction block connected to receive, first, voltage at the terminals of the storage node of a pixel of the corresponding column and, second, a reference voltage of value substantially equal to the reset voltage of the pixels of the matrix seen at the input of the read pathway; the sensor comprises a controller for driving the transistors of pixels and the read circuit to perform an image acquisition in global shutter mode with subtraction of the reset noise and non-destructive reading of the pixels. A method for acquiring images is provided.

Abstract translation: 一种有源像素图像传感器，包括以行和列组织的像素矩阵，以及包括用于每列像素的不同读取路径的读取电路，包括：光电二极管，存储节点，传输晶体管，存储节点复位晶体管， 行选择晶体管和安装为电压跟随器的晶体管; 每个读取通道包括减法模块，其连接用于首先接收相应列的像素的存储节点的端子处的电压，以及第二参考电压，其基本上等于所述矩阵的像素的复位电压 在读路径的输入端; 传感器包括用于驱动像素晶体管和读取电路的控制器，以通过减去复位噪声和像素的非破坏性读数来执行全局快门模式中的图像采集。 提供了一种用于获取图像的方法。

公开(公告)号：US09438218B2

公开(公告)日：2016-09-06

申请号：US14815292

申请日：2015-07-31

Applicant: PYXALIS

Inventor： Grégoire Chenebaux

IPC: H03K5/159 ,  G06F13/16 ,  G06F1/10 ,  H03K5/13

CPC classification number: H03K5/159 ,  G06F1/10 ,  G06F13/16 ,  H03K5/133

Abstract: Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays.

Abstract translation: 提供了通过几个相互相同的部分图案的光复制产生的大尺寸的集成电路，更准确地说，涉及从一个部分电路到随后的信号（特别是时钟信号）的传播延迟的补偿，而有关的信号必须到达各种部分电路 同时为整体正常运行。 在每个部分电路中提供的补偿电路包括用于主时钟信号的主传输线和具有多个输出的补偿线，以及用于选择一个输出的多路复用器，所选择的输出在各种局部电路中是不同的。 多路复用器在每个部分电路中提供本地时钟信号，尽管传播延迟，这些时钟信号是同步的。

公开(公告)号：US20160134290A1

公开(公告)日：2016-05-12

申请号：US14933915

申请日：2015-11-05

Applicant: PYXALIS

Inventor： Pierre-Adrien PINONCELY

IPC: H03K23/00 ,  H03M1/36 ,  H03K4/06

CPC classification number: H03K23/005 ,  H03K4/06 ,  H03M1/36 ,  H03M7/16

Abstract: An N-bit Gray counter, with N an integer greater than 1, comprises a string of N logic cells connected in cascade, wherein each logic cell comprises an input port for a succession of clock pulses, a circuit for generating a Gray count bit having an output port for the Gray count bit and a circuit for generating a clock signal having a clock output port linked to the input port of the following logic cell. An analogue-digital converter of ramp type using such a Gray counter is also provided.

Abstract translation: N为大于1的整数的N位灰计数器包括串联连接的N个逻辑单元的串，其中每个逻辑单元包括用于一系列时钟脉冲的输入端口，用于产生具有 用于灰色计数位的输出端口和用于产生具有链接到以下逻辑单元的输入端口的时钟输出端口的时钟信号的电路。 还提供了使用这种灰色计数器的斜坡型模拟数字转换器。

公开(公告)号：US20220337765A1

公开(公告)日：2022-10-20

申请号：US17719297

申请日：2022-04-12

Applicant: PYXALIS

Inventor： Marie GUILLON

IPC: H04N5/347 ,  H04N5/378 ,  H04N5/3745 ,  H04N5/353

Abstract: A pixel matrix includes a sub-matrix of four adjacent pixels. Each of the pixels of the sub-matrix comprises: a set of a photoelectric-effect element and a memory point, a detection node, a transfer gate. The binning stage is connected to the set and is common with an adjacent pixel of the sub-matrix. At least one detection node per sub-matrix is common to two adjacent pixels of the sub-matrix. The pixel matrix furthermore comprises at least one readout stage per sub-matrix, connected to the common detection node.