利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.028 秒)

    Systems and methods for effectively interacting with a flash memory
    1.
    发明授权
    Systems and methods for effectively interacting with a flash memory 有权

    公开(公告)号：US09690713B1

    公开(公告)日：2017-06-27

    申请号：US14690433

    申请日：2015-04-19

    申请人： Parallel Machines Ltd.

    发明人： Lior Khermosh ,  Ofer Bar-Or ,  Gal Zuckerman

    IPC分类号： G06F12/0893 ,  G06F3/06

    CPC分类号： G06F3/0679 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0862 ,  G06F2003/0691 ,  G06F2212/2022

    摘要： Various systems and methods to use a plurality of linked lists for keeping track of changes to be made in data sets currently in a flash memory. To enhance efficiency of the system, the changes to be made in any particular data set are aggregated in a random access memory (“RAM”) until a sufficient volume of changes have been aggregated to justify a rewrite of the flash memory block in which the particular data set is stored. Since a flash memory may have millions of memory blocks and data sets, there are potentially tremendous demands on the memory resources of the RAM to keep track of all the changes, but the problem presented by these potential demands is avoided through the use of linked lists, in which each list links all of the changes that have been aggregated in RAM and that apply to one specific data set.

    Systems and methods for executing actions using cached data
    4.
    发明授权
    Systems and methods for executing actions using cached data 有权
    使用缓存数据执行操作的系统和方法

    公开(公告)号：US09594688B1

    公开(公告)日：2017-03-14

    申请号：US14806861

    申请日：2015-07-23

    申请人： Parallel Machines Ltd.

    发明人： Michael Adda ,  Avner Braverman ,  Lior Amar ,  Lior Khermosh ,  Gal Zuckerman

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/1081 ,  G06F13/4022 ,  G06F17/30412 ,  G06F2212/1024 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/6026

    摘要： Described herein are systems and methods to execute efficiently a plurality of actions, in which multiple actions require the use of a single data set. The data set is fetched from a data source, across a switching network, to a memory associated with a first compute element. This is the only fetching of the data set from the data source, and the only fetching across a switching network, thereby minimizing fetching across the switching network, reducing the load on the switching network, decreasing the time by which the data set will be accessed in second and subsequent processes, and enhancing the efficiency of the system. In some embodiments, processes are migrated from second and subsequent compute elements to the compute element in which the data set is stored. In some embodiments, second and subsequent compute elements access the data set stored in the memory associated with the first compute element.

    摘要翻译： 这里描述了有效执行多个动作的系统和方法，其中多个动作需要使用单个数据集。 将数据集从数据源跨越交换网络提取到与第一计算元件相关联的存储器。 这是从数据源中唯一获取数据集，并且仅通过交换网络获取数据集，从而最小化跨交换网络的提取，减少交换网络上的负载，减少数据集将被访问的时间 在第二和后续过程中，并提高系统的效率。 在一些实施例中，将进程从第二计算元素和后续计算元素迁移到存储数据集的计算元素。 在一些实施例中，第二和随后的计算元件访问存储在与第一计算元件相关联的存储器中的数据集。

    Systems and methods to communicate with external destinations via a memory network
    7.
    发明授权
    Systems and methods to communicate with external destinations via a memory network 有权

    公开(公告)号：US09781027B1

    公开(公告)日：2017-10-03

    申请号：US14676937

    申请日：2015-04-02

    申请人： Parallel Machines Ltd.

    发明人： Avner Braverman ,  Ofir Shalvi ,  Lior Khermosh ,  Ofer Bar-Or ,  Eyal Benjamin Raz Oren ,  Gal Zuckerman

    IPC分类号： G06F15/167 ,  H04L12/727 ,  H04L29/08

    CPC分类号： G06F13/16 ,  G06F15/173 ,  H04L67/1097

    摘要： Various systems and methods to facilitate general communication, via a memory network, between compute elements and external destinations, while at the same time facilitating low latency communication between compute elements and memory modules storing data sets, without impacting negatively the latency of the communication between the compute elements and the memory modules. General communication messages between compute nodes and a gateway compute node are facilitated with a first communication protocol adapted for low latency transmissions. Such general communication messages are then transmitted to external destinations with a second communication protocol that is adapted for the general communication network and which may or may not be low latency, but such that the low latency between the compute elements and the memory modules is not negatively impacted. The memory modules may be based on RAM or DRAM or another structure allowing low latency access by the compute elements.

    Systems and methods for automatic generation of task-splitting code
    8.
    发明授权
    Systems and methods for automatic generation of task-splitting code 有权
    用于自动生成任务分解代码的系统和方法

    公开(公告)号：US09529622B1

    公开(公告)日：2016-12-27

    申请号：US14740885

    申请日：2015-06-16

    申请人： Parallel Machines Ltd.

    发明人： Michael Adda ,  Avner Braverman ,  Lior Amar ,  Lior Khermosh ,  Eli Finer ,  Gal Zuckerman

    IPC分类号： G06F12/08 ,  G06F9/48 ,  G06F13/16 ,  G06F9/50 ,  G06F9/46

    CPC分类号： G06F9/542 ,  G06F8/10 ,  G06F8/451 ,  G06F9/461 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/5066 ,  G06F9/544 ,  G06F11/3624 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/1081 ,  G06F13/1663 ,  G06F2212/2532

    摘要： Various systems and methods to generate automatically a procedure operative to divide a processing task between two or more compute elements. A first compute element converts a code sequence into a sequence of executable instructions, which direct a second compute element to perform a first processing sub-task on a data set, and which also direct a third compute element to perform a second processing sub-task on the data set modified by the first processing sub-task. A memory module storing the data set may be embedded in a server with at least one of the compute elements. In some of the embodiments, all of the compute elements are part of a single system, whereas in alternative embodiments, at least some of the compute elements are part of two or more sub-systems.

    摘要翻译： 自动产生用于在两个或多个计算元件之间划分处理任务的程序的各种系统和方法。 第一计算元件将代码序列转换成可执行指令序列，其引导第二计算元件在数据集上执行第一处理子任务，并且还引导第三计算元件执行第二处理子任务 对由第一个处理子任务修改的数据集。 存储数据集的存储器模块可以被嵌入到具有至少一个计算元件的服务器中。 在一些实施例中，所有计算元件都是单个系统的一部分，而在替代实施例中，至少一些计算元件是两个或多个子系统的一部分。

    Systems and methods for automatically aggregating write requests
    10.
    发明授权
    Systems and methods for automatically aggregating write requests 有权
    自动聚合写入请求的系统和方法

    公开(公告)号：US09477412B1

    公开(公告)日：2016-10-25

    申请号：US14806835

    申请日：2015-07-23

    申请人： Parallel Machines Ltd.

    发明人： Lior Amar ,  Gal Zuckerman ,  Avner Braverman ,  Lior Khermosh ,  Michael Adda

    IPC分类号： G06F3/06 ,  G06F13/40 ,  G06F12/10 ,  G06F17/30

    CPC分类号： G06F12/0862 ,  G06F3/0611 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/1081 ,  G06F13/4022 ,  G06F17/30412 ,  G06F2212/1024 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/6026

    摘要： Described herein are various systems and methods to automatically decide to aggregate data write requests in a distributed data store. A system initiates outgoing data write requests in synchronization with incoming data store commands, thereby facilitating low-latency read-back of the data. In response to an absence of data read requests, the system automatically changes such that each request includes two or more data sets, thereby breaking synchronization but consequently reducing traffic load on a switching network within the system. If the system later detects data read requests for previously stored data, the system will automatically change back to the original synchronized state, thereby decreasing the latency of accessing stored data. The system alternates between the modes of operation to achieve balance between low latency of data access and reduced traffic load on the switching network.

    摘要翻译： 这里描述了自动决定在分布式数据存储中聚合数据写入请求的各种系统和方法。 系统与传入的数据存储命令同步地启动输出数据写入请求，从而有助于数据的低延迟读取。 响应于没有数据读取请求，系统自动改变，使得每个请求包括两个或更多个数据集，从而破坏同步，但是因此减少系统内的交换网络上的业务负载。 如果系统稍后检测到先前存储的数据的数据读取请求，则系统将自动切换回原始同步状态，从而减少访问存储数据的延迟。 该系统在操作模式之间交替，以实现数据访问的低延迟和交换网络上的减少的流量负载之间的平衡。