公开(公告)号：US20090091358A1

公开(公告)日：2009-04-09

申请号：US12006091

申请日：2007-12-28

Applicant: Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

Inventor： Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

IPC: H03B1/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions. The slew rate control circuit consists of two separate slew rate control circuits called a pull-up PMOS driver and a pull-down NMOS driver. To minimize the variations in the slew rate, the rising and falling time of the pre-driver nodes are controlled by means of two current control networks, which are compensated against PVT variations by using separate NMOS and PMOS digital compensation codes. The compensation codes are provided by a compensation circuit, which sense the variation in PVT conditions and reflect these variations in the compensation codes.

Abstract translation: 本发明提供一种补偿输出缓冲电路，其提供改进的转换速率控制和用于最小化缓冲器在过程，电压和温度（PVT）条件下的电流转换速率的变化的方法。 输出缓冲电路包括分闸门补偿驱动器和转换速率控制电路。 因此，可以在PVT条件的宽泛变化范围内以较少的变化来维持期望的转换速率。 转换速率控制电路由两个单独的转换速率控制电路组成，称为上拉PMOS驱动器和下拉式NMOS驱动器。 为了最小化转换速率的变化，预驱动器节点的上升和下降时间通过两个电流控制网络来控制，这两个电流控制网络通过使用单独的NMOS和PMOS数字补偿代码来补偿PVT变化。 补偿代码由补偿电路提供，该补偿电路检测PVT条件的变化并反映补偿代码中的这些变化。

公开(公告)号：US08207754B2

公开(公告)日：2012-06-26

申请号：US12391944

申请日：2009-02-24

Applicant: Paras Garg ,  Saiyid Mohammad Irshad Rizvi

Inventor： Paras Garg ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract translation: IO面板和性能方面针对广泛的驱动器级别进行了优化的IO缓冲器模块，包括IO单元模块和至少一个IO加法器模块，可操作地耦合到所述IO单元模块，以使IO缓冲模块能够在宽范围 驱动级别。 IO加法器模块可以以多种不同的组合添加IO单元模块，以提供宽范围的驱动电平，并且IO缓冲模块可以提供从1 mA到10 mA或更高的驱动解决方案，步长为0.5 mA 驱动级别。

公开(公告)号：US20120086469A1

公开(公告)日：2012-04-12

申请号：US13106982

申请日：2011-05-13

Applicant: Paras Garg ,  Saiyid Mohammed Irshad Rizvi

Inventor： Paras Garg ,  Saiyid Mohammed Irshad Rizvi

IPC: H03K19/003

CPC classification number: H03K5/04

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract translation: 通过提取输入信号的AC分量并将其叠加在公共参考电压上以产生所得到的电压来减小偏斜。 所产生的电压被提供给比较器的输入，比较器将其与参考电压进行比较以提供最终的输出。 因此，根据实施例，馈送到系统的所有信号在相同的DC电平处被参考，因此减少了偏斜。

公开(公告)号：US07902885B2

公开(公告)日：2011-03-08

申请号：US12006091

申请日：2007-12-28

Applicant: Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

Inventor： Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

IPC: H03B19/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: The disclosure relates a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions.

Abstract translation: 本公开涉及提供改进的转换速率控制的补偿输出缓冲电路和用于最小化缓冲器在过程，电压和温度（PVT）条件下的电流转换速率的变化的方法。 输出缓冲电路包括分闸门补偿驱动器和转换速率控制电路。 因此，可以在PVT条件的宽泛变化范围内以较少的变化来维持期望的转换速率。

公开(公告)号：US20080111580A1

公开(公告)日：2008-05-15

申请号：US11897520

申请日：2007-08-30

Applicant: Ankit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

Inventor： Ankit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

IPC: H03K17/16

CPC classification number: H03K17/6872 ,  H03K17/04206 ,  H03K17/0822 ,  H03K17/165

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract translation: 一种用于在驱动传输线负载的CMOS缓冲器的状态转变期间改善输出的输出缓冲器电路。 电路产生与负载传输线阻抗成比例的可变输出阻抗。 缓冲器包括输出级，例如用于接收输入信号并产生输出信号的上拉/下拉驱动器。 上拉/下拉驱动器由产生控制信号的电路偏置，并根据控制信号改变其电导率。 上拉/下拉驱动器最初提供相对较低的阻抗以在输出的初始过渡期间达到期望的电平，然后响应于控制信号缓慢地改变其阻抗以抑制振铃效应。 控制电路耦合到输入节点，输出节点和电源节点，以产生偏置上拉/下拉驱动器的控制信号。

公开(公告)号：US07368976B2

公开(公告)日：2008-05-06

申请号：US11290619

申请日：2005-11-29

Applicant: Sushil K. Gupta ,  Paras Garg

Inventor： Sushil K. Gupta ,  Paras Garg

IPC: H03K3/01

CPC classification number: H03K3/011 ,  H03K3/3565 ,  H03K17/145 ,  H03K19/00384

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

Abstract translation: 在本发明中，提出了一种用于对MOS电路中的温度，工艺和电源电压变化进行补偿的装置和方法。 本发明提供过程，温度和电压检测电路的变化，其控制CMOS电路中的器件的体偏置和驱动。 检测电路与要控制的CMOS电路的任何输入或内部信号无关。

公开(公告)号：US20060017482A1

公开(公告)日：2006-01-26

申请号：US11148947

申请日：2005-06-09

Applicant: Virender Chauhan ,  Paras Garg

Inventor： Virender Chauhan ,  Paras Garg

IPC: H03K3/037

CPC classification number: H03K3/3565

Abstract: A compensated Schmitt Trigger circuit for providing a monotonic hysterisis response, the circuit including a plurality of transistors connected in series and coupled to a common input signal at their control inputs, a feedback circuit connected to the output of the plurality of transistors, an inverter coupled to the output of the plurality of transistors and to the feedback circuit for providing a hysterisis response at higher supply voltage, wherein the feedback circuit includes at least one feedback element coupled between the output of said plurality of transistors and input of the inverter for providing a monotonic hysterisis response at the output node of the Schmitt Trigger circuit. The feedback elements are connected/disconnected by control signals that reflect the variations in PVT conditions, and the control signals are derived from the standard Input/Output circuits library for compensation.

Abstract translation: 一种用于提供单调滞后响应的补偿施密特触发电路，该电路包括串联连接并耦合到其控制输入处的公共输入信号的多个晶体管，连接到多个晶体管的输出端的反馈电路， 耦合到多个晶体管的输出端和反馈电路，用于在较高的电源电压下提供滞后响应，其中反馈电路包括耦合在所述多个晶体管的输出和反相器的输入端之间的至少一个反馈元件， 施密特触发电路输出节点的单调滞后响应。 反馈元件通过反映PVT条件变化的控制信号连接/断开，控制信号从标准输入/输出电路库导出，用于补偿。

公开(公告)号：US08253437B2

公开(公告)日：2012-08-28

申请号：US13106982

申请日：2011-05-13

Applicant: Paras Garg ,  Saiyid Mohammad Irshad Rizvi

Inventor： Paras Garg ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K5/04

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract translation: 通过提取输入信号的AC分量并将其叠加在公共参考电压上以产生所得到的电压来减小偏斜。 所产生的电压被提供给比较器的输入，比较器将其与参考电压进行比较以提供最终的输出。 因此，根据实施例，馈送到系统的所有信号在相同的DC电平处被参考，因此减少了偏斜。

公开(公告)号：US20100213980A1

公开(公告)日：2010-08-26

申请号：US12391944

申请日：2009-02-24

Applicant: Paras Garg ,  Saiyid Mohammad Irshad Rizvi

Inventor： Paras Garg ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0175 ,  H03K19/094

CPC classification number: H03K19/017509

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract translation: IO面板和性能方面针对广泛的驱动器级别进行了优化的IO缓冲器模块，包括IO单元模块和至少一个IO加法器模块，可操作地耦合到所述IO单元模块，以使IO缓冲模块能够在宽范围 驱动级别。 IO加法器模块可以以多种不同的组合添加单元模块，以提供宽范围的驱动电平，并且IO缓冲模块可以提供从1 mA到10 mA或更高的驱动解决方案，步长为0.5 mA驱动 水平。

公开(公告)号：US07768311B2

公开(公告)日：2010-08-03

申请号：US11897520

申请日：2007-08-30

Applicant: Amit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

Inventor： Amit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

IPC: H03K17/16 ,  H03K19/094

CPC classification number: H03K17/6872 ,  H03K17/04206 ,  H03K17/0822 ,  H03K17/165

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract translation: 一种用于在驱动传输线负载的CMOS缓冲器的状态转变期间改善输出的输出缓冲器电路。 电路产生与负载传输线阻抗成比例的可变输出阻抗。 缓冲器包括输出级，例如用于接收输入信号并产生输出信号的上拉/下拉驱动器。 上拉/下拉驱动器由产生控制信号的电路偏置，并根据控制信号改变其电导率。 上拉/下拉驱动器最初提供相对较低的阻抗以在输出的初始过渡期间达到期望的电平，然后响应于控制信号缓慢地改变其阻抗以抑制振铃效应。 控制电路耦合到输入节点，输出节点和电源节点，以产生偏置上拉/下拉驱动器的控制信号。