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公开(公告)号：US08093103B2
公开(公告)日：2012-01-10
申请号：US12907023
申请日：2010-10-18
Applicant: Rey H. Bruce , Ricardo H. Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
Inventor： Rey H. Bruce , Ricardo H. Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
CPC classification number: H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。
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公开(公告)号：US20110038127A1
公开(公告)日：2011-02-17
申请号：US12907023
申请日：2010-10-18
Applicant: Rey BRUCE , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
Inventor： Rey BRUCE , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
CPC classification number: H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。
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公开(公告)号：US07826243B2
公开(公告)日：2010-11-02
申请号：US11322442
申请日：2005-12-29
Applicant: Rey Bruce , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
Inventor： Rey Bruce , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
IPC: G11C5/02
CPC classification number: H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。
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