Multi-pass system and method supporting multiple streams of video
    3.
    发明授权
    Multi-pass system and method supporting multiple streams of video 有权
    支持多视频流的多通道系统和方法

    公开(公告)号:US07990390B2

    公开(公告)日:2011-08-02

    申请号:US10386313

    申请日:2003-03-11

    IPC分类号: G06T1/20 G06T1/00 G06F15/16

    CPC分类号: G06F13/28 H04N21/426

    摘要: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

    摘要翻译: 公开了用于在网络中执行数据的多个处理的系统和方法。 在一个实施例中,网络包括从多个可能的显示管道实时形成并且对接收到的数据执行至少第一处理步骤的第一显示管道。 缓冲器存储经处理的数据,并且从多个可能的显示管道实时形成的第二显示管道对存储的数据执行至少第二处理步骤。

    Methods and apparatus for collapsing interrupts
    4.
    发明授权
    Methods and apparatus for collapsing interrupts 失效
    破坏中断的方法和装置

    公开(公告)号:US07861104B2

    公开(公告)日:2010-12-28

    申请号:US10004458

    申请日:2001-10-23

    IPC分类号: G06F1/12

    CPC分类号: G06F9/4812 G06F21/602

    摘要: Methods and apparatus are provided for generating interrupts associated with the completion of data processing. An external host may pass a first data block to a first processing engine and later pass a second data block to a second processing engine. In typical implementations, the external host expects that processing of the first data block completes first. To prevent errors and faults on the part of the external host, an interrupt associated with the processing of the second data block completing first is collapsed onto the first data block.

    摘要翻译: 提供了用于产生与完成数据处理相关联的中断的方法和装置。 外部主机可以将第一数据块传递给第一处理引擎,然后将第二数据块传递给第二处理引擎。 在典型的实现中,外部主机期望第一数据块的处理首先完成。 为了防止外部主机的错误和故障,与首先完成的第二数据块的处理相关联的中断被折叠到第一数据块上。

    Video bus for a video decoding system
    5.
    发明授权
    Video bus for a video decoding system 失效
    用于视频解码系统的视频总线

    公开(公告)号:US07853734B2

    公开(公告)日:2010-12-14

    申请号:US10386245

    申请日:2003-03-11

    IPC分类号: G06F13/00

    CPC分类号: G06T9/00

    摘要: Systems and methods are disclosed for a bus, link or interface. More specifically, systems and methods are discloses for a bus, link or interface adapted to transmit data and control information to at least one processing module and provide synchronization between the data and the control information without requiring the transmission of blank pixels or timing information.

    摘要翻译: 公开了一种总线,链路或接口的系统和方法。 更具体地,公开了一种用于总线,链路或接口的系统和方法,适于将数据和控制信息发送到至少一个处理模块,并且在数据和控制信息之间提供同步,而不需要发送空白像素或定时信息。

    Filter module for a video decoding system
    6.
    发明授权
    Filter module for a video decoding system 失效
    用于视频解码系统的滤波模块

    公开(公告)号:US07636125B2

    公开(公告)日:2009-12-22

    申请号:US10386312

    申请日:2003-03-11

    IPC分类号: H04N7/01 H04N3/27 H04N5/268

    摘要: Systems and methods are disclosed for filter modules in a video display system or network. One embodiment relates to a method for operating a filter module in a video display network comprising determining a picture type, display type and operation of the display network. The method further comprises determining, in real time, a filter configuration from a plurality of possible filter configurations based on the determined picture type, display type and operation.

    摘要翻译: 公开了用于视频显示系统或网络中的滤波器模块的系统和方法。 一个实施例涉及一种在视频显示网络中操作滤波器模块的方法,包括确定显示网络的图像类型,显示类型和操作。 该方法还包括基于所确定的图像类型,显示类型和操作,实时地确定来自多个可能的滤波器配置的滤波器配置。

    Memory controller with ring bus for interconnecting memory clients to memory devices
    7.
    发明申请
    Memory controller with ring bus for interconnecting memory clients to memory devices 有权
    具有环形总线的内存控制器,用于将内存客户端连接到内存设备

    公开(公告)号:US20080016254A1

    公开(公告)日:2008-01-17

    申请号:US11484191

    申请日:2006-07-11

    IPC分类号: G06F15/16

    CPC分类号: G06F13/1657

    摘要: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic

    摘要翻译: 描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。 在一个实施例中,在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控​​制器包括环形总线,用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个 设备。 环形总线被配置为分布在集成电路器件的一部分上的环形形状,导致存储器控制器中心处的最大布线密度的降低。 环形总线结构还减少了互连的总数以及存储元件的数量,从而减少了存储器控制器使用的总面积。 环形总线通过位于集成电路设备上的存储器件接口电路将物理上位于集成电路上的环形拓扑内的存储器客户端耦合到外部存储器件。 存储器控制器还包括使用环形总线上的虚拟通道用于一个或多个定义类型的总线业务的死锁避免机制

    Method and system for converting interlaced formatted video to progressive scan video
    8.
    发明授权
    Method and system for converting interlaced formatted video to progressive scan video 失效
    将隔行格式化视频转换为逐行扫描视频的方法和系统

    公开(公告)号:US07113221B2

    公开(公告)日:2006-09-26

    申请号:US10634459

    申请日:2003-08-04

    IPC分类号: H04N11/20

    摘要: Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the binder. A selector may also be coupled to the 3:2 cadence processor. A memory and a processor may also be coupled to any of the 3:2 pull down detector, the 3:2 cadence processor, the color edge detector, the binder, the filter and said output selector. The selector may select between a filtered deinterlaced output and a reverse 3:2 pull down output.

    摘要翻译: 本发明的方面包括耦合到3:2节奏处理器的3:2下拉检测器和耦合到粘合剂的颜色边缘检测器。 绑定器可以耦合到3:2节奏处理器。 可以是时间或无限脉冲响应滤波器的滤波器可以耦合到粘合剂。 选择器也可以耦合到3:2节奏处理器。 存储器和处理器也可以耦合到3:2下拉检测器,3:2节奏处理器,色边检测器,装订器,滤波器和所述输出选择器中的任何一个。 选择器可以在滤波的去隔行输出和反向3:2下拉输出之间进行选择。

    Method and system for detecting diagonal strength of an edge in an image
    9.
    发明申请
    Method and system for detecting diagonal strength of an edge in an image 有权
    用于检测图像边缘对角线强度的方法和系统

    公开(公告)号:US20050168654A1

    公开(公告)日:2005-08-04

    申请号:US10945645

    申请日:2004-09-21

    IPC分类号: H04N5/14

    CPC分类号: H04N5/142

    摘要: A system and method that determines the strength of an edge in a video image using a gradient of the edge in a first direction and a gradient of the edge in a second direction. The system uses the gradient in the first direction and the gradient in the second direction to approximate a distance function to determine the strength of the edge. A programmable threshold may be used in the determination, where an edge is treated like it does not exist if the distance is less than the threshold. The distance function may be an approximation of the Cartesian distance function.

    摘要翻译: 一种使用第一方向上的边缘的梯度和沿第二方向的边缘的梯度来确定视频图像中的边缘的强度的系统和方法。 系统使用第一方向的梯度和第二方向的梯度近似距离函数来确定边缘的强度。 可以在确定中使用可编程阈值,其中如果距离小于阈值,则边缘被处理像不存在。 距离函数可以是笛卡尔距离函数的近似值。