公开(公告)号：US08607003B2

公开(公告)日：2013-12-10

申请号：US13183776

申请日：2011-07-15

申请人： Patrick M. Bland ,  Dhruv M. Desai ,  Jimmy G. Foster, Sr. ,  Makoto Ono

发明人： Patrick M. Bland ,  Dhruv M. Desai ,  Jimmy G. Foster, Sr. ,  Makoto Ono

IPC分类号： G06F12/06 ,  G06F13/378

CPC分类号： G06F9/3824 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/305 ,  G06F2212/311

摘要： Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.

摘要翻译： 提供了用于存储器访问双列直插存储器模块（DIMM）形状因子闪存的方法，装置和计算机程序产品。 实施例包括由控制器从处理器通过处理器中的可缓存存储器接收读取请求; 由控制器将读请求传送到DIMM外形闪存; 由控制器轮询DIMM形状因子闪存中的读取队列，直到数据准备好读取请求; 通过控制器将与DIMM读写请求对应的数据从DIMM形状因子闪存复制到控制器中的读取队列; 由控制器在控制器和处理器之间的接口上发送用于可缓存存储器的无效命令; 并且响应于接收到无效命令，由处理器读取存储在控制器中的读取队列中的数据。

公开(公告)号：US07562247B2

公开(公告)日：2009-07-14

申请号：US11434611

申请日：2006-05-16

申请人： Marcus A. Baker ,  Justin P. Bandholz ,  Patrick M. Bland ,  Andrew S. Heinzmann

发明人： Marcus A. Baker ,  Justin P. Bandholz ,  Patrick M. Bland ,  Andrew S. Heinzmann

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/1604 ,  G06F11/20

摘要： Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.

摘要翻译： 公开了用于为可伸缩刀片服务器提供独立的时钟故障切换的方法和系统，包括将服务器刀片分配给多个时钟故障转移组中的一个，向服务器刀片的时钟发生器提供多个独立的时钟信号，其中， 多个独立时钟信号是活动时钟信号，检测分配给服务器刀片的时钟故障切换组的故障转移条件，并响应于检测到的故障转移条件将活动时钟信号从一个独立时钟信号切换到另一独立时钟 信号。

公开(公告)号：US5561820A

公开(公告)日：1996-10-01

申请号：US351220

申请日：1994-11-30

申请人： Patrick M. Bland ,  Daniel R. Cronin, III ,  Richard G. Hofmann ,  Dennis Moeller ,  Lance M. Venarchick

发明人： Patrick M. Bland ,  Daniel R. Cronin, III ,  Richard G. Hofmann ,  Dennis Moeller ,  Lance M. Venarchick

IPC分类号： G06F13/28 ,  G06F13/40

CPC分类号： G06F13/28 ,  G06F13/4027

摘要： A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.

摘要翻译： 用于计算机系统中总线的桥接口具有控制计算机系统中的存储器传输的直接存储器访问（DMA）控制器。 DMA控制器具有一对提供多个DMA通道的级联DMA控制器芯片。 多路复用器电路从DMA控制器芯片接收存储器地址信号。 存储器地址信号在多路复用器输入端以移位形式和非移相形式被接收。 通过选择多路复用器处的移位或未移位的存储器地址，在多路复用器输出处产生偶数或奇数地址，用于每个DMA通道，由此选择性地提供8位或16位存储器访问。 多路复用器的控制可针对每个DMA通道进行编程，提供DHA通道作为8位或16位通道的动态配置。

公开(公告)号：US5522064A

公开(公告)日：1996-05-28

申请号：US590978

申请日：1990-10-01

申请人： Alfredo Aldereguia ,  Daryl C. Cromer ,  Patrick M. Bland ,  Rodger M. Stutes

发明人： Alfredo Aldereguia ,  Daryl C. Cromer ,  Patrick M. Bland ,  Rodger M. Stutes

IPC分类号： G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F1/06 ,  G06F1/04 ,  G06F1/08

CPC分类号： G06F13/4243

摘要： A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs (Single In-line Memory Modules) that differ in size and speed of operation. The memory controller is operable, in response to an access request for a given SIMM, to read from a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS (Row Address Strobe) to CAS (Column Address Strobe) time, and CAS pulse width, depending on the SIMM being accessed.

摘要翻译： 数据处理系统包括存储器控制器，用于访问动态存储器，该动态存储器具有大小和操作速度不同的多个SIMM（单列直插存储器模块）。 响应于给定SIMM的访问请求，存储器控制器可操作地从SIMM定义寄存器读取并且根据所访问的特定SIMM的定时要求动态地产生存储器访问信号。 每次访问SIMM时都会设置这些信号。 这些信号根据正在访问的SIMM提供RAS预充电时间，RAS（行地址选通）到CAS（列地址选通）时间的不同时钟周期和CAS脉冲宽度。

公开(公告)号：US5450551A

公开(公告)日：1995-09-12

申请号：US68477

申请日：1993-05-28

申请人： Nader Amini ,  Patrick M. Bland ,  Bechara F. Boury ,  Richard G. Hofmann ,  Terence J. Lohman

发明人： Nader Amini ,  Patrick M. Bland ,  Bechara F. Boury ,  Richard G. Hofmann ,  Terence J. Lohman

IPC分类号： G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/364

CPC分类号： G06F13/4018 ,  G06F13/30 ,  G06F13/36

摘要： A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

摘要翻译： 提供直接存储器访问（DMA）支持机制用于计算机系统，其包括（i）通过第一系统总线连接到系统存储器的中央处理单元（CPU）和连接到CPU的第二系统总线; （ii）将第二系统总线连接到外围总线的主桥; （iii）将外围总线连接到标准I / O总线的输入/输出（I / O）桥，标准I / O总线具有连接到其上的多个标准I / O设备; 以及（v）以仲裁模式起作用的仲裁逻辑，用于在竞争访问标准I / O总线的多个标准I / O设备之间进行仲裁，并且在授权模式中，授权选择的标准I / O设备被授权访问 到标准I / O总线。 DMA支持机制包括代表所选标准I / O设备执行DMA周期的直接存储器访问（DMA）控制器，以及直接存储器访问（DMA）支持逻辑，用于通过外设总线执行DMA周期。 DMA支持逻辑包括直接连接DMA控制器与I / O桥的边带信号，边带信号包括识别DMA控制器正在执行DMA周期的所选I / O设备的总线大小的信息。

公开(公告)号：US5182809A

公开(公告)日：1993-01-26

申请号：US358810

申请日：1989-05-31

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Philip E. Milling

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Philip E. Milling

IPC分类号： G06F12/08

CPC分类号： G06F12/0888

摘要： A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：US5045998A

公开(公告)日：1991-09-03

申请号：US359794

申请日：1989-06-01

申请人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

发明人： Ralph M. Begun ,  Patrick M. Bland ,  Mark E. Dean

IPC分类号： G06F12/08

CPC分类号： G06F12/0888

摘要： A microprocessor system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

摘要翻译： 采用80386 CPU和82385高速缓存控制器的微处理器系统具有动态总线大小调整功能（CPU与可能或不是32位宽的设备交互）以及发布的写入功能。 不幸的是，如果将写周期发布到在单个周期内不能传输32位的器件，则这两个功能具有不兼容的可能性。 本发明提供了克服这种不兼容性的逻辑。 提供地址解码器来解码在CPU总线上断言的地址的标签部分，以确定所断言的地址是否在限定可高速缓存设备的地址范围之内或之外。 任何可缓存设备的定义为32位宽，因此发布的写入仅允许可缓存设备。 因此，采用本发明的微计算机系统将写入周期写入可高速缓存的设备; 对不可缓存设备的写周期被禁止发布。

公开(公告)号：US20130166849A1

公开(公告)日：2013-06-27

申请号：US13525002

申请日：2012-06-15

申请人： Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

发明人： Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

IPC分类号： G06F12/00

CPC分类号： G06F15/167

摘要： A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect.

公开(公告)号：US20130166672A1

公开(公告)日：2013-06-27

申请号：US13334237

申请日：2011-12-22

申请人： Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

发明人： Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

IPC分类号： G06F15/167

CPC分类号： G06F15/167

摘要： A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect.

摘要翻译： 一种具有物理上远程共享计算机存储器的计算系统，所述计算系统包括：远程存储器管理模块，多个计算设备，在所述多个计算设备外部的多个远程存储器模块以及远程存储器控制器， 远程存储器管理模块被配置为在多个计算设备之间划分物理上远程的共享计算机存储器; 每个计算设备包括计算机处理器和本地存储器控制器，所述本地存储器控制器包括：处理器接口，本地存储器接口和本地互连接口; 每个远程存储器控制器包括：远程存储器接口和远程互连接口，其中远程存储器控制器经由远程互连接口可操作地耦合到数据通信互连，使得远程存储器控制器被耦合用于与本地存储器控制器的数据通信 通过数据通信互连。

公开(公告)号：US20130019048A1

公开(公告)日：2013-01-17

申请号：US13183776

申请日：2011-07-15

申请人： Patrick M. Bland ,  Dhruv M. Desai ,  Jimmy G. Foster, SR. ,  Makoto Ono

发明人： Patrick M. Bland ,  Dhruv M. Desai ,  Jimmy G. Foster, SR. ,  Makoto Ono

IPC分类号： G06F12/02

CPC分类号： G06F9/3824 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/305 ,  G06F2212/311

摘要： Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.

摘要翻译： 提供了用于存储器访问双列直插存储器模块（DIMM）形状因子闪存的方法，装置和计算机程序产品。 实施例包括由控制器从处理器通过处理器中的可缓存存储器接收读取请求; 由控制器将读请求传送到DIMM外形闪存; 由控制器轮询DIMM形状因子闪存中的读取队列，直到数据准备好读取请求; 通过控制器将与DIMM读写请求对应的数据从DIMM形状因子闪存复制到控制器中的读取队列; 由控制器在控制器和处理器之间的接口上发送用于可缓存存储器的无效命令; 并且响应于接收到无效命令，由处理器读取存储在控制器中的读取队列中的数据。