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1.发明授权Semiconductor structure having wide and narrow deep trenches with different materials 失效半导体结构具有宽而窄的深沟槽，具有不同的材料公开(公告)号：US08652933B2
公开(公告)日：2014-02-18
申请号：US12943973
申请日：2010-11-11
申请人： Paul C. Parries , Yanli Zhang
发明人： Paul C. Parries , Yanli Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material.
摘要翻译： 公开了一种在半导体层中形成半导体器件结构的方法。 该方法包括在半导体层中形成第一宽度的第一沟槽和第二宽度的第二沟槽; 沉积符合第一沟槽的壁但不填充它并填充第二沟槽的第一材料层; 从第一沟槽去除第一材料，第一材料残留在第二沟槽中; 在所述第二沟槽中沉积第二材料并填充所述第一沟槽并且覆盖所述第一材料的顶部; 并且从所述第二沟槽中的所述第一材料的顶部均匀地去除所述第二材料，其中所述第一沟槽被所述第二材料填充，并且所述第二沟槽被所述第一材料填充，并且其中所述第一材料与所述第二材料不同。
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公开(公告)号：US08652925B2
公开(公告)日：2014-02-18
申请号：US12838515
申请日：2010-07-19
IPC分类号： H01L21/20
CPC分类号： H01L21/2007 , G06F17/5068 , H01L21/76224 , H01L21/7624 , H01L21/76251 , H01L21/76283 , H01L21/84 , H01L27/0207 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L27/1203 , H01L28/40 , H01L28/90 , H01L29/66181
摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。
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3.发明授权Structure and method for forming isolation and buried plate for trench capacitor 有权用于形成沟槽电容器的隔离和掩埋板的结构和方法公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。
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4.发明授权公开(公告)号：US08536649B2
公开(公告)日：2013-09-17
申请号：US13608860
申请日：2012-09-10
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。
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公开(公告)号：US20130043559A1
公开(公告)日：2013-02-21
申请号：US13211570
申请日：2011-08-17
申请人： JUNEDONG LEE , Xi Li , Paul C. Parries , Richard Wise , Hongwen Yan
发明人： JUNEDONG LEE , Xi Li , Paul C. Parries , Richard Wise , Hongwen Yan
CPC分类号： H01L29/66181 , H01L21/3065 , H01L21/3081
摘要： A method includes removing an exposed portion of a first portion of a substrate to define a first trench portion partially defined by the first portion of the substrate and expose a second portion of the substrate, the first portion of the substrate disposed on the second portion of the substrate, the second portion of the substrate including an N+ doped silicon material, and removing a portion the exposed second portion of the substrate with an isotropic etching process to define a second trench portion.
摘要翻译： 一种方法包括去除衬底的第一部分的暴露部分以限定部分地由衬底的第一部分限定并且暴露衬底的第二部分的第一沟槽部分，衬底的第一部分设置在衬底的第二部分上 衬底，衬底的第二部分包括N +掺杂的硅材料，并且用各向同性蚀刻工艺去除衬底的暴露的第二部分的一部分以限定第二沟槽部分。
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6.发明授权Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权SOI衬底中的深沟槽电容器具有横向突出的埋入带公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。
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公开(公告)号：US07791124B2
公开(公告)日：2010-09-07
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译： 用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。 在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。 采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。 深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。 在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。 或者，可以在形成掩埋带之前去除电介质间隔物。
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公开(公告)号：US07705386B2
公开(公告)日：2010-04-27
申请号：US11969989
申请日：2008-01-07
IPC分类号： H01L27/108 , H01L21/8244
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。
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公开(公告)号：US20090289291A1
公开(公告)日：2009-11-26
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译： 用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。 在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。 采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。 深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。 在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。 或者，可以在形成掩埋带之前去除电介质间隔物。
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公开(公告)号：US07564729B2
公开(公告)日：2009-07-21
申请号：US12057011
申请日：2008-03-27
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。
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