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公开(公告)号：US08440917B2
公开(公告)日：2013-05-14
申请号：US11942061
申请日：2007-11-19
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译： 一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。
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公开(公告)号：US20130075148A1
公开(公告)日：2013-03-28
申请号：US13426892
申请日：2012-03-22
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译： 一种具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。
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公开(公告)号：US08338949B2
公开(公告)日：2012-12-25
申请号：US13369273
申请日：2012-02-08
申请人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
CPC分类号： H01L23/645 , H01L21/563 , H01L23/295 , H01L23/49816 , H01L23/552 , H01L2224/13022 , H01L2224/73203 , H01L2924/01077 , H01L2924/3011 , H05K1/0233 , H05K2201/10977 , Y10T29/49147
摘要： A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
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公开(公告)号：US20120138349A1
公开(公告)日：2012-06-07
申请号：US13369273
申请日：2012-02-08
申请人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
IPC分类号： H05K1/02
CPC分类号： H01L23/645 , H01L21/563 , H01L23/295 , H01L23/49816 , H01L23/552 , H01L2224/13022 , H01L2224/73203 , H01L2924/01077 , H01L2924/3011 , H05K1/0233 , H05K2201/10977 , Y10T29/49147
摘要： A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
摘要翻译： 改进核心封装连接的系统可以包括球栅阵列焊盘和球栅阵列。 该系统还可以包括导电连接到相应的球栅阵列焊盘的球栅阵列的连接构件。 该系统还可以包括邻近至少一些连接构件和相应的球栅阵列垫定位的磁性底部填充，以增加各自的连接构件的电感。
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公开(公告)号：US20090126983A1
公开(公告)日：2009-05-21
申请号：US11942061
申请日：2007-11-19
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译： 一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。
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6.发明授权Systems and methods for reducing simultaneous switching noise in an integrated circuit 失效用于降低集成电路中同时开关噪声的系统和方法公开(公告)号：US07492570B2
公开(公告)日：2009-02-17
申请号：US11105113
申请日：2005-04-13
申请人： Eiichi Hosomi , Paul M. Harvey
发明人： Eiichi Hosomi , Paul M. Harvey
IPC分类号： H01G4/228
CPC分类号： H01L23/50 , H01L23/13 , H01L23/49838 , H01L23/562 , H01L2924/0002 , H01L2924/15311 , H01L2924/19106 , H01L2924/3511 , H05K1/0231 , H05K1/182 , H05K2201/09072 , H05K2201/1053 , H05K2201/10734 , H01L2924/00
摘要： Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.
摘要翻译： 用于降低集成电路中的开关噪声的系统和方法。 在一个实施例中，去耦电容器从其上制造集成电路芯片的基板的下侧连接到集成电路。 去耦电容器在集成电路的“热点”区域中以更高的浓度定位，而不是均匀分布。 在一个实施例中，在其上安装集成电路的电路板中的去耦电容器和相应的孔定位成使得电路板为集成电路的中心部分提供支撑，从而防止集成电路弯曲 远离散热器/吊具。 在一个实施例中，连接集成电路内的不同接地层和/或电源层的通孔的浓度在热点中高于其它区域。
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公开(公告)号：US07064412B2
公开(公告)日：2006-06-20
申请号：US09491302
申请日：2000-01-25
IPC分类号： H01L21/00
CPC分类号： H01L23/49838 , H01L23/49833 , H01L23/50 , H01L23/642 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01038 , H01L2924/0104 , H01L2924/0105 , H01L2924/01056 , H01L2924/01073 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic package including a conductive trace layer having a first side and a second side. The conductive trace layer is patterned to define a plurality of interconnect pads. A flexible dielectric substrate is mounted on the first side of the conductive trace layer. A flexible capacitor including a first conductive layer, a second conductive layer and a layer of dielectric material disposed between the first and the second conductive layers is mounted with the first conductive layer adjacent to the second side of the conductive trace layer. A plurality of interconnect regions extend through the first conductive layer and the dielectric material layer of the capacitor. An interconnect member is connected between each one of the conductive layers of the capacitor and a corresponding set of the interconnect pads. The first conductive layer of the capacitor is electrically connected to a first set of the interconnect pads and the second conductive layer of the capacitor is electrically connected to a second set of the interconnect pads. The interconnect members corresponding to the second set of interconnect pads extend through one of the interconnect regions. An aperture extends through the dielectric substrate adjacent to each one of the interconnect pads. A stiffening member is mounted adjacent to the second conductive layer of the capacitor. A device receiving region is formed through the dielectric substrate, the conductive trace layer and the capacitor.
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公开(公告)号：US6140707A
公开(公告)日：2000-10-31
申请号：US74126
申请日：1998-05-07
申请人： Anthony R. Plepys , Paul M. Harvey
发明人： Anthony R. Plepys , Paul M. Harvey
IPC分类号： H01L23/12 , H01L21/50 , H01L23/498 , H01L29/40
CPC分类号： H01L21/50 , H01L23/49816 , H01L23/4985 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/07811 , H01L2924/15311
摘要： A low-cost integrated circuit package is provided for packaging integrated circuits. In preferred embodiments, the package comprises a flexible circuit that is laminated to a stiffener using a dielectric adhesive, with the conductive traces on the flexible circuit facing toward the stiffener but separated therefrom by the adhesive. The conductive traces include an array of flip-chip attachment pads. A window is formed in the stiffener over the attachment pad array, such as by etching. The adhesive is then removed over the attachment pads by laser ablation, but left in place between the pads, thus forming a flip-chip attachment site. In preferred embodiments, this invention eliminates the need for high-resolution patterned adhesive, and it also eliminates the need for application of a solder mask at the flip-chip attachment site, because the remaining adhesive performs the solder mask function of preventing bridging between attachment pads. This package provides a die attachment site having a high degree of planarity due to tensile stresses formed in the flexible circuit and adhesive layers during lamination of those layers to the stiffener. Embodiments of this invention may be used with TBGA, frangible lead, and other packaging technologies.
摘要翻译： 提供了一种用于封装集成电路的低成本集成电路封装。 在优选实施例中，封装包括使用电介质粘合剂层压到加强件的柔性电路，柔性电路上的导电迹线面向加强件，但是通过粘合剂与其分离。 导电迹线包括倒装芯片附接焊盘的阵列。 在附着垫阵列上的加强件中形成窗口，例如通过蚀刻。 然后通过激光烧蚀在粘附垫上去除粘合剂，但留在垫之间的位置，从而形成倒装芯片附着部位。 在优选实施例中，本发明消除了对高分辨率图案化粘合剂的需要，并且也消除了在倒装芯片附接位置处施加焊接掩模的需要，因为剩余的粘合剂执行阻焊功能以防止附着之间的桥接 垫 该包装提供了由于在将这些层层压到加强件期间在柔性电路和粘合剂层中形成的拉伸应力而具有高度平坦度的模具附接部位。 本发明的实施例可以与TBGA，易碎引线和其他封装技术一起使用。
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公开(公告)号：US08791372B2
公开(公告)日：2014-07-29
申请号：US13426892
申请日：2012-03-22
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译： 具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。
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公开(公告)号：US08631706B2
公开(公告)日：2014-01-21
申请号：US12840861
申请日：2010-07-21
CPC分类号： G01L9/12 , H01L2224/16227 , H01L2224/16235 , H01L2924/1531 , H01L2924/3025 , H05K1/0228 , H05K1/0231 , H05K1/0251 , Y10T29/49139 , Y10T29/49142
摘要： One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.
摘要翻译： 一个或多个去耦电容器耦合到低电感安装座，该低电感安装件连接到其上安装有半导体模块的印刷电路板（PCB）的底层。 低电感安装座包括磁性平面结构，其具有耦合到一个或多个去耦电容器的过孔以及位于PCB上的相似通孔。
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