Delay adjustment circuit in a performance monitoring and test system
    1.
    发明授权
    Delay adjustment circuit in a performance monitoring and test system 失效
    性能监测和测试系统中的延迟调整电路

    公开(公告)号:US5875217A

    公开(公告)日:1999-02-23

    申请号:US452347

    申请日:1995-05-26

    摘要: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

    摘要翻译: 用于电话网络的DS3级别访问,监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1,DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路(FDL)处理程序。 与本发明的系统中提供1:1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。

    Frame synchronization in a performance monitoring and test system
    2.
    发明授权
    Frame synchronization in a performance monitoring and test system 失效
    性能监控和测试系统中的帧同步

    公开(公告)号:US5557616A

    公开(公告)日:1996-09-17

    申请号:US450494

    申请日:1995-05-26

    摘要: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

    摘要翻译: 用于电话网络的DS3级别访问,监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1,DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路(FDL)处理程序。 与本发明的系统中提供1:1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。

    Remote module for a communications network
    3.
    发明授权
    Remote module for a communications network 有权
    用于通信网络的远程模块

    公开(公告)号:US06910167B2

    公开(公告)日:2005-06-21

    申请号:US10223232

    申请日:2002-08-15

    摘要: Determination of the location of an error condition or a failure includes receiving at a network interface a first framed digital signal from customer premises equipment, and determining whether the first framed digital signal indicates a failure. Overhead bits are modified in the first framed digital signal to generate a second framed digital signal, such that the modification is equivalent to insertion of errors into the first framed digital signal at a bit error ratio (BER) of not greater than a predetermined ratio, if the first framed digital signal indicates a failure. The second framed digital signal is then sent from the network interface in place of the first framed digital signal to indicate that the failure reported by the first framed digital signal is located in the customer premises equipment. Otherwise, if no failure is indicated, the first framed digital signal is transmitted without any modifications.

    摘要翻译: 确定错误状况或故障的位置包括在网络接口处接收来自客户驻地设备的第一帧数字信号,以及确定第一帧数字信号是否指示故障。 在第一成帧数字信号中修改开销比特以产生第二成帧数字信号,使得修改等效于以不大于预定比率的误码率(BER)将误差插入到第一成帧数字信号中, 如果第一个成帧的数字信号指示故障。 然后,第二帧数字信号从网络接口代替第一帧数字信号,以指示由第一帧数字信号报告的故障位于客户驻地设备中。 否则,如果没有指示故障,则第一帧数字信号被传输而不作任何修改。

    Performance monitoring and test system for a telephone network
    6.
    发明授权
    Performance monitoring and test system for a telephone network 失效
    电话网络的性能监控和测试系统

    公开(公告)号:US5691976A

    公开(公告)日:1997-11-25

    申请号:US118443

    申请日:1993-09-07

    摘要: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

    摘要翻译: 用于电话网络的DS3级别访问,监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1,DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路(FDL)处理程序。 与本发明的系统中提供1:1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。

    Performance monitoring and test system for a telephone network
    7.
    发明授权
    Performance monitoring and test system for a telephone network 失效
    电话网络的性能监控和测试系统

    公开(公告)号:US5956324A

    公开(公告)日:1999-09-21

    申请号:US960775

    申请日:1997-10-30

    摘要: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

    摘要翻译: 用于电话网络的DS3级别访问,监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1,DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路(FDL)处理程序。 与本发明的系统中提供1:1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。

    Facilities data link handler in a performance monitoring and test system
    10.
    发明授权
    Facilities data link handler in a performance monitoring and test system 失效
    在性能监视和测试系统中设置数据链接处理程序

    公开(公告)号:US5703871A

    公开(公告)日:1997-12-30

    申请号:US451172

    申请日:1995-05-26

    摘要: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

    摘要翻译: 用于电话网络的DS3级别访问,监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1,DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路(FDL)处理程序。 与本发明的系统中提供1:1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。