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    Integrated circuits that include deep trench capacitors and methods for their fabrication
    1.
    发明授权
    Integrated circuits that include deep trench capacitors and methods for their fabrication 有权
    集成电路包括深沟槽电容器及其制造方法

    公开(公告)号：US08853810B2

    公开(公告)日：2014-10-07

    申请号：US13218262

    申请日：2011-08-25

    申请人： Peter Baars ,  Till Schloesser

    发明人： Peter Baars ,  Till Schloesser

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L49/02

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91

    摘要： Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

    摘要翻译： 提供了用于制造包括深沟槽电容器的集成电路的方法。 一种方法包括在半导体衬底上制造多个晶体管，所述多个晶体管各自包括栅极结构，源极和漏极区以及到源极和漏极区的硅化物接触。 然后在所选择的晶体管的漏极区域附近将沟槽蚀刻到半导体衬底中。 沟槽填充有与半导体衬底接触的金属层，覆盖金属层的电介质材料层和覆盖在介电材料层上的第二金属。 然后形成金属接触，将第二金属耦合到所选晶体管的漏极区上的硅化物接触。 与所选择的晶体管的源极区域接触的位线形成为与晶体管的栅极结构接触的字线。

    Method of removing gate cap materials while protecting active area
    4.
    发明授权
    Method of removing gate cap materials while protecting active area 有权
    在保护有源区域的同时去除栅极盖材料的方法

    公开(公告)号：US08697557B2

    公开(公告)日：2014-04-15

    申请号：US13154521

    申请日：2011-06-07

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/31053 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底之上形成栅电极结构，其中栅电极结构包括栅极绝缘层，栅极电极，靠近栅电极定位的第一侧壁隔离物和栅极盖层，以及形成 栅极覆盖层上方的蚀刻停止层，以及靠近栅电极结构的衬底上方的蚀刻停止层。 该方法还包括在蚀刻停止层上方形成间隔物材料层，以及执行至少一个第一平面化处理以去除位于栅极电极上方的所述隔离层材料层的部分，所述蚀刻停止层的部分位于 栅电极和栅极帽层。

    Encapsulation of closely spaced gate electrode structures
    6.
    发明授权
    Encapsulation of closely spaced gate electrode structures 有权
    密封间隔栅电极结构的封装

    公开(公告)号：US08647952B2

    公开(公告)日：2014-02-11

    申请号：US12974037

    申请日：2010-12-21

    申请人： Peter Baars ,  Richard Carter ,  Andy Wei

    发明人： Peter Baars ,  Richard Carter ,  Andy Wei

    IPC分类号： H01L21/336

    CPC分类号： H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.

    摘要翻译： 通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

    INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF
    7.
    发明申请
    INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF 审中-公开
    集成电路，包括铜线互连及其制造方法

    公开(公告)号：US20130193489A1

    公开(公告)日：2013-08-01

    申请号：US13361644

    申请日：2012-01-30

    申请人： Peter Baars ,  Erik P. Geiss

    发明人： Peter Baars ,  Erik P. Geiss

    IPC分类号： H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76895 ,  H01L21/28518 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/11

    摘要： Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors.

    摘要翻译： 提供了一种用于制造集成电路的方法的实施例。 在一个实施例中，制造了部分制造的集成电路，其包括具有源极/漏极区域的半导体衬底，以及包括形成在半导体衬底之上和源极/漏极区域之间的多个栅极导体的多个晶体管。 器件级触点形成为与栅极导体和源极/漏极区域欧姆接触。 器件级触点在半导体衬底上方基本相同的水平处终止。 然后，铜互连线形成在器件级触点上方并与其欧姆接触，以局部地互连多个晶体管。

    STI silicon nitride cap for flat FEOL topology
    8.
    发明授权
    STI silicon nitride cap for flat FEOL topology 有权
    STI氮化硅帽用于平面FEOL拓扑

    公开(公告)号：US08415214B2

    公开(公告)日：2013-04-09

    申请号：US13010110

    申请日：2011-01-20

    申请人： Frank Jakubowski ,  Peter Baars ,  Jörg S. Radecker

    发明人： Frank Jakubowski ,  Peter Baars ,  Jörg S. Radecker

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/84

    摘要： Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode.

    摘要翻译： 在FEOL处理期间，晶体管器件在STI区域上形成有氮化物盖。 实施例包括在衬底上形成焊盘氧化物层，在衬底中形成STI区，使得顶表面与衬垫氧化物的顶表面平齐，在STI区上形成氮化物盖，并在衬垫氧化物的一部分 在STI区域的每一侧上的层，将掺杂剂注入到衬底中，使氮化物帽和衬垫氧化物层脱气，去除氮化物帽，以及去除衬垫氧化物层。 实施例包括在放置焊盘氧化物层之前在衬底中形成硅锗沟道（c-SiGe）。 氮化物帽在趋向于降低STI氧化物的工艺期间保护STI区域和紧邻区域，从而为随后沉积的高k电介质和金属电极提供基本上无刮痕的衬底和具有零阶高度的STI区域。

    Method of Forming Metal Silicide Regions on a Semiconductor Device
    10.
    发明申请
    Method of Forming Metal Silicide Regions on a Semiconductor Device 有权
    在半导体器件上形成金属硅化物区域的方法

    公开(公告)号：US20130015527A1

    公开(公告)日：2013-01-17

    申请号：US13180655

    申请日：2011-07-12

    申请人： Hans-Juergen Thees ,  Peter Baars

    发明人： Hans-Juergen Thees ,  Peter Baars

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4232 ,  H01L29/4975 ,  H01L29/78

    摘要： The present disclosure is directed to various methods of forming metal silicide regions on an integrated circuit device. In one example, the method includes forming a PMOS transistor and an NMOS transistor, each of the transistors having a gate electrode and at least one source/drain region formed in a semiconducting substrate, forming a first sidewall spacer adjacent the gate electrodes and forming a second sidewall spacer adjacent the first sidewall spacer. The method further includes forming a layer of material above and between the gate electrodes, wherein the layer of material has an upper surface that is positioned higher than an upper surface of each of the gate electrodes, performing a first etching process on the layer of material to reduce a thickness thereof such that the upper surface of the layer of material is positioned at a desired level that is at least below the upper surface of each of the gate electrodes, and after performing the first etching process, performing a second etching process to insure that a desired amount of the gate electrodes for the PMOS transistor and the NMOS transistor are exposed for a subsequent metal silicide formation process. The method concludes with the step of forming metal silicide regions on the gate electrode structures and on the source/drain regions.

    摘要翻译： 本公开涉及在集成电路器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括形成PMOS晶体管和NMOS晶体管，每个晶体管具有栅极电极和形成在半导体衬底中的至少一个源极/漏极区域，形成邻近栅电极的第一侧壁间隔物并形成 邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括在栅电极之上和之间形成一层材料，其中该材料层具有位于每个栅电极的上表面的上表面，对该材料层进行第一蚀刻工艺 为了减小其厚度，使得材料层的上表面位于至少低于每个栅电极的上表面的期望水平，并且在执行第一蚀刻工艺之后，执行第二蚀刻工艺 确保用于PMOS晶体管和NMOS晶体管的期望量的栅电极暴露于随后的金属硅化物形成工艺。 该方法的结论是在栅极电极结构和源极/漏极区域上形成金属硅化物区域的步骤。