公开(公告)号：US20090265201A1

公开(公告)日：2009-10-22

申请号：US12426678

申请日：2009-04-20

申请人： Min Sik KIM ,  Jung Gil PARK ,  Soon Jwa HONG ,  Peter Hoh In ,  Taek LEE

发明人： Min Sik KIM ,  Jung Gil PARK ,  Soon Jwa HONG ,  Peter Hoh In ,  Taek LEE

IPC分类号： G06Q10/00

CPC分类号： G06Q40/06

摘要： Provided are a method and apparatus for determining a security solution. The method and apparatus generate a security solution analysis model for analyzing effects on investment of security solution combinations consisting of several security solution candidates on the basis of integer programming (IP), standardize various constraints that have significant effects on security solution determination on the basis of IP, and apply the standardized constraints to the security solution analysis model, thereby determining a security solution combination having the smallest residual risk while satisfying the constraints as an optimum security solution combination.According to the method and apparatus, an optimum security solution combination that can minimize a residual risk while satisfying various constraints is rapidly and accurately determined. Thus, it is possible to support effective determination in information security investment.

摘要翻译： 提供了一种用于确定安全解决方案的方法和装置。 该方法和设备生成一个安全解决方案分析模型，用于分析由基于整数规划（IP）的几个安全解决方案候选者组成的安全解决方案组合对投资的影响，标准化对基于安全解决方案确定有重大影响的各种约束 IP，并将标准化约束应用于安全解决方案分析模型，从而确定具有最小剩余风险的安全解决方案组合，同时满足约束作为最佳安全解决方案组合。 根据该方法和装置，可以快速，准确地确定在满足各种约束的情况下最小化剩余风险的最佳安全解决方案组合。 因此，有可能支持信息安全投资的有效决定。

公开(公告)号：US06548357B2

公开(公告)日：2003-04-15

申请号：US10117869

申请日：2002-04-08

申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：US06486505B1

公开(公告)日：2002-11-26

申请号：US09535445

申请日：2000-03-24

申请人： Thomas S. Rupp ,  Jeffrey P. Gambino ,  Peter Hoh ,  Senthil Srinivasan

发明人： Thomas S. Rupp ,  Jeffrey P. Gambino ,  Peter Hoh ,  Senthil Srinivasan

IPC分类号： H01L27108

CPC分类号： H01L27/10873

摘要： In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.

摘要翻译： 一方面，本发明公开了一种晶体管器件（参见例如图3），其包括设置在半导体本体122中并由通道区域128a隔开的第一和第二源极/漏极区域124a和126。 电介质层134a覆盖在沟道区128a上，栅电极130a / 132a覆盖在电介质层134a上。 在优选实施例中，栅电极包括在电介质层上延伸第一横向距离的多晶硅层130a和在第一多晶硅层上延伸第二横向距离的硅化物层132a。 在该示例中，第一横向距离大于第二横向距离。

公开(公告)号：US06228279B1

公开(公告)日：2001-05-08

申请号：US09156065

申请日：1998-09-17

申请人： Michael Armacost ,  Peter Hoh ,  Richard S. Wise ,  Wendy Yan

发明人： Michael Armacost ,  Peter Hoh ,  Richard S. Wise ,  Wendy Yan

IPC分类号： H01L213065

CPC分类号： H01L21/31138

摘要： By providing a photoresist material with a protective polymer layer during the etching of an organic anti-reflective coating, undue damage to the photoresist material can be avoided during opening of the anti-reflective coating without the need for an oxidant. The preferred polymer chemistry system for producing such a result includes a fluorohydrocarbon-containing polymer mixture with a strong source of CF3, preferably C2F6. The etchant also includes a source of hydrogen selected from CH3F, C2HF5, or CH2F2, and a diluent selected from Ar, He or N2.

摘要翻译： 在蚀刻有机抗反射涂层期间通过提供具有保护性聚合物层的光致抗蚀剂材料，可以在打开抗反射涂层期间避免对光致抗蚀剂材料的过度损坏而不需要氧化剂。 用于产生这种结果的优选聚合物化学体系包括具有强的CF 3源，优选C 2 F 6的含氟代烃的聚合物混合物。 蚀刻剂还包括选自CH 3 F，C 2 H 5或CH 2 F 2的氢源和选自Ar，He或N 2的稀释剂。

公开(公告)号：US06403423B1

公开(公告)日：2002-06-11

申请号：US09713272

申请日：2000-11-15

申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些电介质间隔物允许阵列栅极导体抗蚀剂线被制成 - 小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。