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公开(公告)号:US08388782B2
公开(公告)日:2013-03-05
申请号:US12788832
申请日:2010-05-27
申请人: Paul S. Andry , Bing Dang , John Knickerbocker , Aparna Prahbakar , Peter J. Sorce , Robert E. Trzcinski , Cornelia K. Tsang
发明人: Paul S. Andry , Bing Dang , John Knickerbocker , Aparna Prahbakar , Peter J. Sorce , Robert E. Trzcinski , Cornelia K. Tsang
CPC分类号: H01L21/67132 , C09J5/06 , C09J2203/326 , C09J2479/08 , H01L21/6835 , H01L2221/6835 , H01L2221/68381 , Y10T156/1158
摘要: A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.
摘要翻译: 一种用于将处理器附接到晶片的方法,所述晶片包括集成电路(IC),包括在所述晶片上形成粘合剂层,所述粘合剂包括基于聚酰亚胺的聚合物,所述聚酰亚胺基聚合物构造成经受超过约280℃的温度下的加工 C。; 以及使用所述粘合剂层将处理器粘附到所述晶片。 一种用于将处理器附接到晶片的系统,包括IC的晶片包括位于晶片上的粘合剂层,所述粘合剂包括基于聚酰亚胺的聚合物,其被配置为经受超过约280℃的温度下的加工; 以及使用粘合剂层粘附到晶片的处理器。
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公开(公告)号:US5231751A
公开(公告)日:1993-08-03
申请号:US784281
申请日:1991-10-29
IPC分类号: H01L23/522 , C08G73/10 , H01L21/48 , H01L21/768 , H01L23/538 , H05K1/05 , H05K3/00 , H05K3/38 , H05K3/40 , H05K3/42 , H05K3/44 , H05K3/46
CPC分类号: H01L23/5384 , H01L21/486 , H01L23/5383 , H05K3/445 , H05K3/4641 , H01L2924/0002 , H05K2201/0154 , H05K2201/068 , H05K2201/09554 , H05K2201/09563 , H05K2201/096 , H05K2203/0152 , H05K3/0032 , H05K3/0035 , H05K3/0061 , H05K3/007 , H05K3/388 , H05K3/4076 , H05K3/423 , H05K3/4614 , H05K3/4617 , Y10T29/49165 , Y10T428/12361 , Y10T428/12382 , Y10T428/12556 , Y10T428/12569 , Y10T428/12806 , Y10T428/12812 , Y10T428/24777 , Y10T428/31678 , Y10T428/31681
摘要: This invention relates generally to a structure and process for thin film interconnect, and more particularly to a structure and process for a multilayer thin film interconnect structure with improved dimensional stability and electrical performance. The invention further relates to a process of fabrication of the multilayer thin film structures. The individual thin film structure is termed a compensator, and functions as both a ground/reference plane and as a stabilizing entity with regard to dimensional integrity. The compensator is comprised primarily of a metal sheet having a metallized via pattern and high-temperature stable polymer as an insulator.
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