公开(公告)号：US20070219772A1

公开(公告)日：2007-09-20

申请号：US11377762

申请日：2006-03-16

Applicant: Alon Kfir ,  Platon Beletsky

Inventor： Alon Kfir ,  Platon Beletsky

IPC: G06F9/455

CPC classification number: G06F17/5022

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract translation: 用于在逻辑仿真系统中仿真存储器电路的方法和装置，包括计算机程序产品。 该系统包括与仿真存储器相关联的至少一个日志存储器。 每个日志存储器位置在预定时间被标记为无效。 系统在预定时间之后接收一个或多个存储器写请求，每个存储器写请求指定要写入指定存储单元的新数据。 如果对应于指定的存储单元的日志存储器位置被标记为无效，则在写入新数据之前，将指定的存储器位置的预写内容复制到相应的日志存储器位置，并且相应的日志存储器位置被标记为有效 在模拟存储器中的指定存储器位置。 通过将标记为有效的每个日志存储器位置的内容复制到仿真存储器来将仿真存储器恢复到预定时间。

公开(公告)号：US07440884B2

公开(公告)日：2008-10-21

申请号：US10373558

申请日：2003-02-24

Applicant: Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

Inventor： Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

IPC: G06F9/455

CPC classification number: G06F17/5027

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract translation: 一种用于调试其中具有随机存取存储器的电路设计的方法和装置。 电路设计在硬件逻辑仿真器上仿真。 由仿真器模拟的RAM可以重绕到先前的状态，然后重播。 由仿真器仿真的RAM也可以被重建为在跟踪窗口期间某个时刻保持RAM的状态。

公开(公告)号：US07555424B2

公开(公告)日：2009-06-30

申请号：US11377762

申请日：2006-03-16

Applicant: Alon Kfir ,  Platon Beletsky

Inventor： Alon Kfir ,  Platon Beletsky

IPC: G06F9/455 ,  G06F11/16

CPC classification number: G06F17/5022

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract translation: 用于在逻辑仿真系统中仿真存储器电路的方法和装置，包括计算机程序产品。 该系统包括与仿真存储器相关联的至少一个日志存储器。 每个日志存储器位置在预定时间被标记为无效。 系统在预定时间之后接收一个或多个存储器写请求，每个存储器写请求指定要写入指定存储单元的新数据。 如果对应于指定的存储单元的日志存储器位置被标记为无效，则在写入新数据之前，将指定的存储器位置的预写内容复制到相应的日志存储器位置，并且相应的日志存储器位置被标记为有效 在模拟存储器中的指定存储器位置。 通过将标记为有效的每个日志存储器位置的内容复制到仿真存储器来将仿真存储器恢复到预定时间。

公开(公告)号：US08352235B1

公开(公告)日：2013-01-08

申请号：US11966602

申请日：2007-12-28

Applicant: Tsair-Chin Lin ,  Bing Zhu ,  Platon Beletsky

Inventor： Tsair-Chin Lin ,  Bing Zhu ,  Platon Beletsky

IPC: G06G7/54 ,  G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F2217/78

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract translation: 一种用于对集成电路（IC）中的功率管理进行建模的方法包括：指定IC的电路设计和电源架构，所述电源架构包括用于指定所述IC的不同部分中的功率电平的多个功率域; 通过包括用于对仿真模块中的电力架构进行建模的一个或多个硬件元件来确定IC的仿真模块; 以及使用所述仿真模块来模拟所述IC的一个或多个功率域中的变化功率水平，包括在至少一个功率域中的功率切断。

公开(公告)号：US06681377B2

公开(公告)日：2004-01-20

申请号：US10246788

申请日：2002-09-17

Applicant: Platon Beletsky

Inventor： Platon Beletsky

IPC: G06F1750

CPC classification number: G06F17/5027 ,  G06F17/505 ,  G06F17/5054

Abstract: A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.

Abstract translation: 一种用于在具有多于一个输入时钟的逻辑设计的时钟锥中重新合成门控时钟的方法，其中逻辑设计将在硬件逻辑仿真系统中实现。 通过重新合成门控时钟，电路中的时序变得可预测。 在该方法中，产生预测所述至少两个输入时钟的哪些边缘的逻辑，可能导致门控时钟上的保持时间违规。 然后，来自预测逻辑的输出连接到门控时钟分辨率电路，其输出再合成时钟。