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    FAN-OUT PACKAGE STRUCTURE OF IMAGE SENSING DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明公开
    FAN-OUT PACKAGE STRUCTURE OF IMAGE SENSING DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230411419A1

    公开(公告)日：2023-12-21

    申请号：US18327449

    申请日：2023-06-01

    申请人： Powertech Technology Inc.

    发明人： Ching-Chao LIN

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14632

    摘要： A fan-out package structure of an image sensing device includes an image sensing unit having an image sensor with opposite sensing surface and connecting surface, a spacer layer surrounding a central portion of the sensing surface, and a light-transmitting cover plate disposed on the spacer layer spaced apart from and covering the sensing surface. An image signal processor is disposed on the connecting surface. A redistribution layer covers the image signal processor and the connecting surface, and includes a fan-out area. An encapsulation layer is disposed on the fan-out area, surrounds and covers an outer periphery of the image sensing unit, and allows a top surface of the light-transmitting cover plate to be exposed. A method of manufacturing a fan-out package structure of an image sensing device is also disclosed.

    PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF
    3.
    发明公开
    PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230290730A1

    公开(公告)日：2023-09-14

    申请号：US18078055

    申请日：2022-12-08

    申请人： POWERTECH TECHNOLOGY INC.

    发明人： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

    IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    CPC分类号： H01L23/5381 ,  H01L23/5383 ,  H01L23/3128 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/568 ,  H01L2224/16227 ,  H01L24/16

    摘要： A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, and at least two active chips. The conductive pillars and the bridge chip are disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer, the active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips.

    Chip carrier device
    7.
    发明授权
    Chip carrier device 有权

    公开(公告)号：US11587808B2

    公开(公告)日：2023-02-21

    申请号：US16998266

    申请日：2020-08-20

    申请人： Powertech Technology Inc.

    发明人： Shih-Chun Chen ,  Sheng-Tou Tseng ,  Kun-Chi Hsu ,  Chin-Ta Wu ,  Ying-Lin Chen ,  Ting-Yeh Wu

    IPC分类号： H01L21/673 ,  C23C14/56

    摘要： A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.

    Package structure and manufacturing method thereof
    8.
    发明授权
    Package structure and manufacturing method thereof 有权

    公开(公告)号：US11545424B2

    公开(公告)日：2023-01-03

    申请号：US16952084

    申请日：2020-11-19

    申请人： Powertech Technology Inc.

    发明人： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

    IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

    摘要： A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.

    Semiconductor package structure and manufacturing method thereof
    9.
    发明授权
    Semiconductor package structure and manufacturing method thereof 有权

    公开(公告)号：US11522000B2

    公开(公告)日：2022-12-06

    申请号：US16856011

    申请日：2020-04-22

    申请人： Powertech Technology Inc.

    发明人： Hung-Hsin Hsu ,  Wen-Hsiung Chang

    IPC分类号： H01L27/14 ,  H01L27/146

    摘要： A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

    Semiconductor package structure with landing pads and manufacturing method thereof
    10.
    发明授权
    Semiconductor package structure with landing pads and manufacturing method thereof 有权

    公开(公告)号：US11437336B2

    公开(公告)日：2022-09-06

    申请号：US16886782

    申请日：2020-05-29

    申请人： Powertech Technology Inc.

    发明人： Jeffrey Wang ,  Jen-I Huang ,  Kun-Yung Huang

    IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    摘要： A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.