公开(公告)号：US20190227979A1

公开(公告)日：2019-07-25

申请号：US16369220

申请日：2019-03-29

Applicant: Brinda Ganesh ,  Yen-Cheng Liu ,  Swadesh Choudhary ,  Tejpal Singh ,  Pradeep Prabhakaran ,  Monam Agarwal

Inventor： Brinda Ganesh ,  Yen-Cheng Liu ,  Swadesh Choudhary ,  Tejpal Singh ,  Pradeep Prabhakaran ,  Monam Agarwal

IPC: G06F15/173 ,  G06F13/40 ,  H01L21/768 ,  H01L25/065

Abstract: In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.