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    Integrated circuit with on chip planar diode and CMOS devices
    2.
    发明授权
    Integrated circuit with on chip planar diode and CMOS devices 有权
    集成电路与片上平面二极管和CMOS器件

    公开(公告)号：US09048108B2

    公开(公告)日：2015-06-02

    申请号：US13478080

    申请日：2012-05-22

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/8238 ,  H01L27/06

    CPC分类号： H01L27/0629 ,  H01L29/0847 ,  H01L29/8611 ,  H01L29/868

    摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

    摘要翻译： 在同一芯片上形成二极管和一个或多个CMOS器件的电路，平面二极管和方法。 该方法包括将二极管区域中的衬底的一部分与其它衬底区域电隔离。 该方法还包括使二极管区域中的衬底凹陷。 该方法还包括在二极管区域中外延形成在衬底上方的第一掺杂层，并在二极管区域中外延地形成第一掺杂层上方的第二掺杂层。

    Junctionless transistor
    5.
    发明授权
    Junctionless transistor 有权
    无结晶体晶体管

    公开(公告)号：US08803233B2

    公开(公告)日：2014-08-12

    申请号：US13242861

    申请日：2011-09-23

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    IPC分类号： H01L29/778

    CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78654 ,  H01L29/78696

    摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

    摘要翻译： 晶体管包括半导体层，并且在半导体层上形成栅极电介质。 栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。 有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。 该渐变掺杂剂区域的掺杂浓度逐渐降低。 晶体管还包括与有源区相邻的源区和漏区。 源极和漏极区域和有源区域具有相同的导电类型。

    Embedded stressors for multigate transistor devices
    6.
    发明授权
    Embedded stressors for multigate transistor devices 失效

    公开(公告)号：US08658505B2

    公开(公告)日：2014-02-25

    申请号：US13325506

    申请日：2011-12-14

    申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

    发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

    摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

    Semiconductor substrate with transistors having different threshold voltages
    7.
    发明授权
    Semiconductor substrate with transistors having different threshold voltages 失效
    具有不同阈值电压的晶体管的半导体衬底

    公开(公告)号：US08642415B2

    公开(公告)日：2014-02-04

    申请号：US13487511

    申请日：2012-06-04

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

    摘要翻译： 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

    MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation
    9.
    发明授权
    MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
    具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源

    公开(公告)号：US08575698B2

    公开(公告)日：2013-11-05

    申请号：US13283308

    申请日：2011-10-27

    申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

    摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.

    摘要翻译： 场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。 嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。 此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

    Inversion mode varactor
    10.
    发明授权
    Inversion mode varactor 有权
    反转模式变容二极管

    公开(公告)号：US08564040B1

    公开(公告)日：2013-10-22

    申请号：US13570360

    申请日：2012-08-09

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L27/108

    CPC分类号： H01L29/93 ,  H01L27/1203 ,  H01L29/66174

    摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.

    摘要翻译： 在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物 半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层， 其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。