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公开(公告)号：US20250070730A1
公开(公告)日：2025-02-27
申请号：US18811986
申请日：2024-08-22
Applicant: Qorvo US, Inc.
Inventor： Marcus Granger-Jones , Shruti Bohara , Toshiaki Moriuchi
IPC: H03F3/24
Abstract: Embodiments of a power amplification device are disclosed. The power amplification device includes a power amplification circuit configured to amplify a radio frequency (RF) input signal and generate an amplified RF output signal. The power amplification device also includes a bias circuit. The bias circuit is provided in a closed loop configuration that has a bipolar junction transistor (BJT) that generates the bias voltage applied to the RF input signal. The BJT is provided in a common emitter configuration. This allows for the bias voltage generated by the bias circuit to be generated with a power voltage having a lower voltage level.
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公开(公告)号：US20250070042A1
公开(公告)日：2025-02-27
申请号：US18802670
申请日：2024-08-13
Applicant: Qorvo US, Inc.
Inventor： Thomas Scott Morris , Mohsen Haji-Rahim , Charles E. Carpenter , Brian Howard Calhoun
IPC: H01L23/552 , H01L21/48 , H01L23/00 , H01L23/538 , H01L25/16
Abstract: The disclosure relates to a shielded electronic module with compartmental integrated shielding. The disclosed shielded electronic module includes an electronic module having an interposer, a mold compound, a first device component, a second device component, and an interior shield wall, and a module shielding structure directly and completely covers a top surface and side surfaces of the electronic module. Herein, the first device component and the second device component are formed over a top surface of the interposer, and the mold compound resides over the top surface of the interposer and fully encapsulates the first device component and the second device component. The interior shield wall is a continuous metal sheet and extends vertically through the mold compound towards the top surface of the interposer to separate the first device component and the second device component. The module shielding structure is physically and electrically connected to the interior shield wall.
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公开(公告)号：US12224717B2
公开(公告)日：2025-02-11
申请号：US17689469
申请日：2022-03-08
Applicant: Qorvo US, Inc.
Inventor： Charles Forrest Campbell
Abstract: Embedded blocking capacitor structures for wideband amplifier circuits are disclosed. A wideband amplifier circuit includes transistors that output radio frequency (RF) signals. An embedded blocking capacitor structure is operably connected between the terminals of the transistors and an RF output. The embedded blocking capacitor structure distributes a bias voltage to the terminals of the transistors and blocks the bias voltage from passing to the RF output. The embedded blocking capacitor structure also propagates an RF signal to an RF output.
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公开(公告)号：US20250044821A1
公开(公告)日：2025-02-06
申请号：US18927360
申请日：2024-10-25
Applicant: Qorvo US, Inc.
Inventor： Toby Balsom , Jeroen Cornelis Kuenen , Vikram Chaturvedi
Abstract: The present disclosure describes a system-on-chip (SoC) including a built-in self-test (BIST) block, a low-dropout (LDO) voltage regulator with a pass metal-oxide semiconductor field-effect transistor (MOSFET), and a current-monitor circuit with a sensing MOSFET, a tuning MOSFET, a sensing resistor, and a tuning resistor. Herein, both the pass MOSFET and the sensing MOSFET receive an input voltage, and a gate of the pass MOSFET is coupled to a gate of the sensing MOSFET. The sensing MOSFET, the tuning MOSFET, and the sensing resistor are connected in series between the input voltage and ground, and the tuning resistor is coupled between a gate of the tuning MOSFET and ground. The BIST block is configured to tune a current through the tuning resistor so as to adjust a voltage at a connection point of the sensing MOSFET and the tuning MOSFET.
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公开(公告)号：US20250015053A1
公开(公告)日：2025-01-09
申请号：US18655986
申请日：2024-05-06
Applicant: Qorvo US, Inc.
Inventor： Tarak A. Railkar , James Edwin Halvorson , Jackline Lew , Walid M. Meliane
IPC: H01L25/065 , H01L21/683 , H01L23/00
Abstract: One aspect of the present disclosure pertains to a method of assembling a flip-chip die stack. The method includes picking a bottom die where the bottom die incudes first interconnect bumps. The method includes placing the bottom die into an opening of a fabrication tool. The bottom die has an exposed portion hovering over an air cavity below the opening. The method includes picking a top die where the top die includes second interconnect bumps. The method includes placing the top die onto the bottom die to form a stacked die structure, inserting the fabrication tool containing the stacked die structure into a reflow oven, and reflowing the stacked die structure. After reflowing the stacked die structure, the second interconnect bumps are bonded to landing pads of the bottom die, and the first interconnect bumps remain unbonded.
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公开(公告)号：US20250006216A1
公开(公告)日：2025-01-02
申请号：US18738803
申请日：2024-06-10
Applicant: Qorvo US, Inc.
Inventor： Andrew Fort
IPC: G10L21/043
Abstract: A method for digital audio conversion is provided. The method includes receiving, at a first sampling rate, a digital audio data stream at a device. The method includes generating, by a clock connected to the device, a second sampling rate, wherein the second sampling rate approximates the first sampling rate by selecting cycles of the clock closest to the cycles of the first sampling rate. The method also includes sampling the digital audio data stream at the second sampling rate to generate a second audio data stream. The method further includes transmitting the second audio data stream to a codec.
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公开(公告)号：US12176855B2
公开(公告)日：2024-12-24
申请号：US17456060
申请日：2021-11-22
Applicant: Qorvo US, Inc.
Inventor： Baker Scott , George Maxim
Abstract: Power amplifiers having improved gate oxide integrity are disclosed. In particular, a dynamic asymmetric cascode bias circuit is used to provide a bias signal to a cascode power amplifier stage. The bias signal swings in synchronicity with an output signal from the power amplifier stage. By having this dynamic bias signal, the gate-drain stress on the device is reduced, preserving gate oxide integrity. Preserving gate oxide integrity helps preserve the operational profile and extend device life, providing an enhanced user experience.
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公开(公告)号：US20240413806A1
公开(公告)日：2024-12-12
申请号：US18812163
申请日：2024-08-22
Applicant: Qorvo US, Inc.
Inventor： Shogo Inoue , Hao Dong
Abstract: An acoustic resonator includes a piezoelectric layer on a substrate and an interdigital electrode structure on the piezoelectric layer. The interdigital electrode structure includes a first bus bar, a second bus bar, a first set of electrode fingers, and a second set of electrode fingers. The first bus bar and the second bus bar extend parallel to one another along a length of the interdigital electrode structure. The first set of electrode fingers are coupled to the first bus bar and extend to a first apodization edge. The second set of electrode fingers are coupled to the second bus bar and extend to a second apodization edge. The first set of electrode fingers and the second set of electrode fingers are interleaved. At least one of the first apodization edge and the second apodization edge provides a wave pattern along the length of the interdigital electrode structure.
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公开(公告)号：US12166466B2
公开(公告)日：2024-12-10
申请号：US16212809
申请日：2018-12-07
Applicant: Qorvo US, Inc.
Inventor： Sebastian Huebner
Abstract: Trim layers that are configured to adjust one or more operating parameters for surface acoustic wave (SAW) devices are disclosed. A SAW device may include an interdigital transducer (IDT) and a piezoelectric material that are configured to generate an acoustic wave and a trim layer that has an acoustic velocity and a density that correspond to a velocity of the acoustic wave. In this manner, the trim layer may be configured to adjust an electromechanical coupling of the SAW device without significantly impacting a resonance frequency of the SAW device. The SAW device may also include an additional trim layer that is configured to adjust a coupling percentage and the resonance frequency of the SAW device. A SAW device may include a trim layer that is configured to adjust certain operating parameters by greater amounts than other operating parameters.
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公开(公告)号：US12166118B2
公开(公告)日：2024-12-10
申请号：US17570600
申请日：2022-01-07
Applicant: Qorvo US, Inc.
Inventor： Edward Beam, III , Jinqiao Xie , Antonio Lucero
IPC: H01L29/778 , H01L29/20 , H01L29/78
Abstract: A layer of yttrium (Y) and aluminum nitride (AlN) is employed as a back-barrier to improve confinement of electrons within a channel layer of a high electron mobility transistor (HEMT). As HEMT dimensions are reduced and a channel length decreases, current control provided by a gate also decreases, and it becomes more difficult to “pinch-off” current flow through the channel. A back-barrier layer on a back side of the channel layer improves confinement of electrons to improve pinch-off but does not cause a second 2DEG to be formed below the back-barrier layer. The YAlN layer can be lattice-matched to the channel layer to avoid lattice strain, and a thin layer of YAlN provides less thermal resistance than HEMTs made with thicker back-barrier materials. Due to its chemical nature, a YAlN layer can be used as an etch stop layer.
