公开(公告)号：US07836257B2

公开(公告)日：2010-11-16

申请号：US11959804

申请日：2007-12-19

申请人： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

发明人： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/128

摘要： A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

摘要翻译： 用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。 第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。 在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行， 第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

公开(公告)号：US20090164735A1

公开(公告)日：2009-06-25

申请号：US11959793

申请日：2007-12-19

申请人： Richard Nicholas ,  Jason Alan Cox ,  Robert John Dorsey ,  Hien Minh Le ,  Eric Francis Robinson ,  Thuong Quang Truong

发明人： Richard Nicholas ,  Jason Alan Cox ,  Robert John Dorsey ,  Hien Minh Le ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

摘要： A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

摘要翻译： 用于维持高速缓存一致性的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有高速缓存，并且每个PU耦合到多个PU中的至少另一个。 第一PU接收用于存储在第一PU的第一高速缓存中的第一数据块。 第一个PU将第一个数据块存储在第一个缓存中。 第一PU将第一相关性状态和第一标签分配给第一数据块，其中第一相关性状态是指示第一PU是否已经访问了第一数据块的多个相关性状态之一。 多个相关性状态还指示在第一PU未访问第一数据块的情况下，第一PU从相邻PU接收到第一数据块。

公开(公告)号：US20090077323A1

公开(公告)日：2009-03-19

申请号：US12273576

申请日：2008-11-19

申请人： Jonathan James DeMent ,  Kerey Michelle Tassin ,  Thuong Quang Truong

发明人： Jonathan James DeMent ,  Kerey Michelle Tassin ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0837 ,  G06F12/0831

摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.

摘要翻译： 创建直写缓存方案。 存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。 然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。 根据存储数据的地址是否有效，将一个直写命令发送到系统总线。 总线控制器用于检测直写命令。 如果感测到直写命令，则总线控制器产生清洁命令。 如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。 如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。

公开(公告)号：US07321956B2

公开(公告)日：2008-01-22

申请号：US10809579

申请日：2004-03-25

申请人： Michael Karl Gschwind ,  Charles Ray Johns ,  Thoung Quang Truong

发明人： Michael Karl Gschwind ,  Charles Ray Johns ,  Thoung Quang Truong

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0817

摘要： A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data items is configured in accordance with one of a plurality of access modes. Each of the plurality of directory information items comprises indicia of the access mode of its associated data item. A multiplexer couples to the memory and comprises a multiplex ratio. A plurality of buffers couple to the multiplexer and to the memory. The multiplex ratio is a function of the number of buffers in the plurality of buffers. A plurality of multiplexer/demultiplexers (MDMs) each uniquely couple to a different one of the plurality of buffers. A plurality of processing elements couple to the memory; each of the processing elements uniquely couples in a point-to-point connection to a different one of the plurality of MDMs. Each of the processing elements is configured to transmit a data request to its associated MDM, the data request identifying one of the plurality of data items and an access mode. Each of the processing elements further comprises a prefetch page cache, the prefetch page cache configured to store a subset of the plurality of data items and the plurality of directory information items. The memory is configured to transmit a data response to each of the processing elements in response to a data request, the data response comprising the identified data item and its associated directory information. Each of the processing elements is farther configured to receive the data response and to compare the associated directory information with the access mode of the data request and in the event that the associated directory information and the access mode of the data request are not compatible, to initiate coherence actions for the requested data item.

公开(公告)号：US20070184775A1

公开(公告)日：2007-08-09

申请号：US11350264

申请日：2006-02-08

申请人： Bernard Perkins ,  Quang Truong ,  Nikhil Gandhi ,  Humberto Meza

发明人： Bernard Perkins ,  Quang Truong ,  Nikhil Gandhi ,  Humberto Meza

IPC分类号： F24F7/00

CPC分类号： F24F7/025 ,  B60H1/262 ,  F24F11/30 ,  F24F11/56 ,  F24F2110/20

摘要： A remote-controlled ventilating system and method. The method can include remotely controlling a ventilation system in a recreational vehicle having a wall and a ceiling. The method can include coupling a fan and a dome to at least one of the wall and the ceiling of the recreational vehicle. The fan and the dome can be connected to a controller. The method can also include transmitting a signal from a remote control to the controller in order to operate the fan and the dome.

摘要翻译： 遥控通风系统及方法。 该方法可以包括在具有墙壁和天花板的休闲车辆中远程控制通风系统。 该方法可以包括将风扇和穹顶连接到休闲车辆的壁和天花板中的至少一个。 风扇和穹顶可以连接到控制器。 该方法还可以包括将信号从遥控器发送到控制器，以便操作风扇和穹顶。

公开(公告)号：US07114035B2

公开(公告)日：2006-09-26

申请号：US10655365

申请日：2003-09-04

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00

CPC分类号： G06F12/126

摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

公开(公告)号：US06230987B1

公开(公告)日：2001-05-15

申请号：US09576975

申请日：2000-05-23

申请人： Hai Quang Truong

发明人： Hai Quang Truong

IPC分类号： A62C502

CPC分类号： A62C5/002 ,  A01C23/042 ,  Y10T137/4891

摘要： An applicator for allowing a predetermined flow of a fluid for dissolving and distributing soluble substances comprises of a cap and a hollow cylindrical housing. The hollow cylindrical housing comprises of an enlarged chamber having a narrowed inlet port at its lower end. The narrowed inlet port has external threads connecting to a Tee pipe fitting of a pipeline of a fluid system and has a cylindrical flow channel extending to the enlarged chamber. The cylindrical flow channel has six equal V flow passages which are constructed by six vertical dividing walls locating at equal spaces around the wall of the cylindrical flow channel and extending inward to the axis of the cylindrical flow channel. The six equal V flow passages have six equal vertical openings which are constructed by the vertical dividing walls and disposed outside the cylindrical flow channel of the narrowed inlet port at a predetermined length. The six equal vertical openings comprises of three vertical inlets and three vertical outlets. The six equal vertical openings have a same bottom wall which is constructed at the lower end of the vertical dividing walls. The same bottom wall has a diameter smaller than the minor diameter of the external threads of the narrowed inlet port.

摘要翻译： 用于允许用于溶解和分配可溶性物质的流体的预定流动的施加器包括盖和中空圆柱形壳体。 中空圆柱形壳体包括在其下端具有变窄的入口的扩大的腔室。 狭窄的入口具有连接到流体系统的管道的T形管接头的外螺纹，并且具有延伸到扩大腔室的圆柱形流动通道。 圆柱形流动通道具有六个相等的V流动通道，其由六个垂直分隔壁构成，六个垂直分隔壁围绕圆柱形流动通道的壁定位在相等的空间处，并向内延伸到圆柱形流动通道的轴线。 六个相等的V流动通道具有六个相等的垂直开口，其由垂直分隔壁构成并且以预定长度设置在狭窄入口的圆柱形流动通道的外侧。 六个相等的垂直开口包括三个垂直入口和三个垂直出口。 六个相同的垂直开口具有相同的底壁，其构造在垂直分隔壁的下端。 相同的底壁的直径小于变窄入口的外螺纹的小直径。

公开(公告)号：US20090164736A1

公开(公告)日：2009-06-25

申请号：US11959804

申请日：2007-12-19

申请人： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

发明人： Robert John Dorsey ,  Jason Alan Cox ,  Hien Minh Le ,  Richard Nicholas ,  Eric Francis Robinson ,  Thuong Quang Truong

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/128

摘要： A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

摘要翻译： 用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。 第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。 在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行， 第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

公开(公告)号：US07472229B2

公开(公告)日：2008-12-30

申请号：US10916969

申请日：2004-08-12

申请人： Jonathan James DeMent ,  Kerey Michelle Tassin ,  Thuong Quang Truong

发明人： Jonathan James DeMent ,  Kerey Michelle Tassin ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0837 ,  G06F12/0831

摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.

摘要翻译： 创建直写缓存方案。 存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。 然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。 根据存储数据的地址是否有效，将一个直写命令发送到系统总线。 总线控制器用于检测直写命令。 如果感测到直写命令，则总线控制器产生清洁命令。 如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。 如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。

公开(公告)号：US07225277B2

公开(公告)日：2007-05-29

申请号：US10655370

申请日：2003-09-04

申请人： Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Quang Truong ,  Asano Shigehiro ,  Takeshi Yamazaki

发明人： Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Quang Truong ,  Asano Shigehiro ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

摘要翻译： 提供了一种用于为第一处理器建立直接存储器访问的系统和方法。 该系统包括第一处理器和本地存储器。 本地存储器耦合到第一处理器。 第一直接存储器存取控制器（DMAC）耦合到第一处理器和本地存储器。 系统存储器与第一DMAC通信。 第二处理器与第一DMAC通信，使得第二处理器设置第一DMAC来处理本地存储器和系统存储器之间的数据传输。 当第一个DMAC完成处理数据传输时，第二个处理器中断。