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公开(公告)号：US20140329476A1
公开(公告)日：2014-11-06
申请号：US14258246
申请日：2014-04-22
Inventor： Shintaro YAMAMICHI , Hirokazu HONDA , Masaki WATANABE , Junichi ARITA , Norio OKADA , Jun UENO , Masashi NISHIMOTO , Michitaka KIMURA , Tomohiro NISHIYAMA
CPC classification number: H04W84/18 , H01L2224/45144 , H01L2224/48091 , H01L2224/49111 , H01L2924/00014 , H01L2924/00
Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
Abstract translation: 作为使用传感器的无线通信系统的组成要素的小型电子设备。 该器件的第一个特征是第一半导体芯片以芯片的形式裸地安装在第一布线板的前表面上，并且第二半导体芯片裸地安装在第二布线板上 芯片的形式。 第二特征是分别安装配置模块的无线通信单元和数据处理单元。 第三特征是第一和第二布线板沿板厚度方向堆叠以组成模块（电子设备）。
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公开(公告)号：US12237254B2
公开(公告)日：2025-02-25
申请号：US17841196
申请日：2022-06-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keita Tsuchiya , Shuuichi Kariyazaki , Kazuhiro Mitamura
IPC: H01L23/498 , H01L23/14 , H01L23/36 , H01L23/367 , H01L23/66 , H01P3/08
Abstract: A wiring substrate includes: a first insulating layer; a ground plane formed on the first insulating layer; a second insulating layer formed on the first insulating layer such that the ground plane is covered with the second insulating layer; a first signal wiring formed on the second insulating layer; a third insulating layer formed on the second insulating layer such that the first signal wiring is covered with the third insulating layer; and a second signal wiring formed on the third insulating layer and electrically connected with the first signal wiring. The first signal wiring is arranged in a region overlapping with a portion of a heat radiating plate. The second signal wiring is not arranged in the region. The ground plane has an opening portion located at a position overlapping with the first signal wiring. The opening portion is formed so as to extend along the first signal wiring.
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公开(公告)号：US20250055471A1
公开(公告)日：2025-02-13
申请号：US18798978
申请日：2024-08-09
Applicant: Renesas Electronics Corporation
Inventor： Tomohiko EBATA , Tetsuo MATSUI
Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.
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公开(公告)号：US20250053191A1
公开(公告)日：2025-02-13
申请号：US18795290
申请日：2024-08-06
Applicant: Renesas Electronics Corporation
Inventor： Yoichi MAEDA , Jun MATSUSHIMA
IPC: G06F1/12
Abstract: The technology provided enables the acceleration of the clock. The semiconductor device comprises a counter circuit configured to generate a read signal when the count number reaches a predetermined number, a buffer configured to store test data and sequentially output the test data in the order stored when the read signal indicates a valid value, and a first scan test circuit that sequentially captures the test data output from the buffer.
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公开(公告)号：US20250040222A1
公开(公告)日：2025-01-30
申请号：US18772473
申请日：2024-07-15
Applicant: Renesas Electronics Corporation
Inventor： Yu NAGAHAMA
IPC: H01L29/40 , H01L21/28 , H01L21/311 , H01L29/423
Abstract: The reliability of the semiconductor device is improved. A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The other part of the field plate electrode FP is selectively retracted toward the bottom of the trench TR so that a part of the field plate electrode FP remains as a lead-out part FPa. A silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation. The insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB and the silicon oxide film OX1 are removed, and the insulating film IF1 is retracted so that its upper surface position is lower than the upper surface position of the field plate electrode FP.
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Patent Agency Ranking
公开(公告)号：US20250037744A1
公开(公告)日：2025-01-30
申请号：US18777820
申请日：2024-07-19
Applicant: Renesas Electronics Corporation
Inventor： Toshiki KIRYU , Toma OGATA , Kosuke YAYAMA , Toyohiro SHIMOGAWA
Abstract: While suppressing the influence of voltage noise, the adjustment range of the power supply voltage generated based on the reference voltage is expanded. The semiconductor device includes a reference voltage generation circuit, a regulator, a buffer, and a voltage control circuit. The reference voltage generation circuit is configured to be able to adjust the reference voltage. The regulator is configured to be able to change the output ratio of the power supply voltage to the reference voltage based on the control signal. The semiconductor device further includes a voltage control circuit for outputting a voltage control signal to the regulator to switch the output ratio.
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公开(公告)号：US12212639B2
公开(公告)日：2025-01-28
申请号：US18384574
申请日：2023-10-27
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Christian Mardmoeller , Dnyaneshwar Kulkarni , Thorsten Hoffleit
IPC: H04L69/08 , H04L12/66 , H04L45/741 , H04L69/18 , H04L45/302 , H04L69/325
Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.
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公开(公告)号：US20250022794A1
公开(公告)日：2025-01-16
申请号：US18768246
申请日：2024-07-10
Applicant: Renesas Electronics Corporation
Inventor： Takayuki IGARASHI , Yasutaka NAKASHIBA
IPC: H01L23/522 , H01L27/02
Abstract: A semiconductor device includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, an insulating layer, and a first shield. The semiconductor substrate has a device region and a peripheral region. The peripheral region is present around the device region in a plan view. The first coil and the second coil are arranged on the device region and are arranged in a first direction in a plan view. The third coil and the fourth coil are respectively opposed to the first coil and the second coil via the insulating layer. The first shield is arranged between the semiconductor substrate and the first and second coils and overlaps with the first coil and the second coil in a plan view. A width of the first shield in a second direction orthogonal to the first direction is larger than a width of the first coil in the second direction and a width of the second coil in the second direction. The first shield is electrically connected to a reference potential.
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公开(公告)号：US20250015200A1
公开(公告)日：2025-01-09
申请号：US18666131
申请日：2024-05-16
Applicant: Renesas Electronics Corporation
Inventor： Keiichi FURUYA
IPC: H01L29/866 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L29/66
Abstract: A semiconductor substrate includes a p-type substrate body, an n-type buried layer on the p-type substrate body, and a p-type semiconductor layer on the n-type buried layer. A DTI region penetrates through the p-type semiconductor layer and the n-type buried layer, and reaches the p-type substrate body. An n-type semiconductor region, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed under the n-type semiconductor region, and a p-type second semiconductor region formed under the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. An impurity concentration of the p-type second semiconductor region is higher than an impurity concentration of the p-type first semiconductor region.
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公开(公告)号：US20250015146A1
公开(公告)日：2025-01-09
申请号：US18763910
申请日：2024-07-03
Applicant: Renesas Electronics Corporation
Inventor： Yotaro GOTO
Abstract: A dielectric film, which contacts a field plate electrode, is formed between the field plate electrode and a gate electrode, and a recess is formed at an upper surface of the dielectric film and between a drain region and the gate electrode.
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