公开(公告)号：US20180089098A1

公开(公告)日：2018-03-29

申请号：US15279319

申请日：2016-09-28

申请人： Francesc Cesc Guim Bernat ,  Kshitij A. Doshi ,  Steen Larsen ,  Mark A. Schmisseur ,  Raj K. Ramanujan

发明人： Francesc Cesc Guim Bernat ,  Kshitij A. Doshi ,  Steen Larsen ,  Mark A. Schmisseur ,  Raj K. Ramanujan

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/0813 ,  G06F12/1441 ,  G06F21/00 ,  G06F2212/1041 ,  G06F2212/657

摘要： Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.

公开(公告)号：US20170187805A1

公开(公告)日：2017-06-29

申请号：US14983087

申请日：2015-12-29

申请人： Francesc Guim Bernet ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Robert G. Blankenship

发明人： Francesc Guim Bernet ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Robert G. Blankenship

IPC分类号： H04L29/08 ,  G06F3/06 ,  G06F9/46

摘要： Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

公开(公告)号：US20170180270A1

公开(公告)日：2017-06-22

申请号：US14973155

申请日：2015-12-17

申请人： Francesc Cesc Guim Bernat ,  Karthik KUMAR ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Narayan Ranganathan

发明人： Francesc Cesc Guim Bernat ,  Karthik KUMAR ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Narayan Ranganathan

IPC分类号： H04L12/931 ,  H04L12/26 ,  H04L1/00 ,  H04L12/927 ,  H04L12/18

CPC分类号： H04L49/201 ,  H04L12/1845 ,  H04L41/5006 ,  H04L43/10 ,  H04L47/806

摘要： Described herein are devices and techniques for distributing application data. A device can communicate with one or more hardware switches. The device can receive, from a software stack, a multicast message including a constraint that indicates how application data is to be distributed. The constraint including a listing of the set of nodes and a number of nodes to which the application data is to be distributed. The device may receive, from the software stack, the application data for distribution to a plurality of nodes. The plurality of nodes being a subset of the set of nodes equaling the number of nodes. The device may select the plurality of nodes from the set of nodes. The device also may distribute a copy of the application data to the plurality of nodes based on the constraint. Also described are other embodiments.

公开(公告)号：US20170031821A1

公开(公告)日：2017-02-02

申请号：US15192871

申请日：2016-06-24

申请人： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Glenn J. HINTON

发明人： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Glenn J. HINTON

IPC分类号： G06F12/0811 ,  G11C14/00 ,  G06F12/0888 ,  G11C7/10 ,  G06F12/02 ,  G06F12/0806

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

摘要翻译： 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制 远记忆 这些更高性能的存储器件被称为“近存储器”。在一个实施例中，“近端存储器”被配置为以多种不同的操作模式操作，包括（但不限于）第一模式，其中近端存储器 作为远存储器的存储器高速缓冲存储器和第二模式，其中近距离存储器被分配有系统地址空间的第一地址范围，远处存储器被分配系统地址空间的第二地址范围，其中第一范围和 第二个范围代表整个系统地址空间。

公开(公告)号：US09378142B2

公开(公告)日：2016-06-28

申请号：US13994731

申请日：2011-09-30

申请人： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/02 ,  G11C7/10 ,  G11C13/00

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

摘要翻译： 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制 远记忆 这些更高性能的存储器件被称为“近存储器”。在一个实施例中，“近端存储器”被配置为以多种不同的操作模式操作，包括（但不限于）第一模式，其中近端存储器 作为远存储器的存储器高速缓冲存储器和第二模式，其中近距离存储器被分配有系统地址空间的第一地址范围，远处存储器被分配系统地址空间的第二地址范围，其中第一范围和 第二个范围代表整个系统地址空间。

公开(公告)号：US20150006834A1

公开(公告)日：2015-01-01

申请号：US13931875

申请日：2013-06-29

申请人： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

发明人： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

IPC分类号： G06F3/06

CPC分类号： G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

摘要： An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

摘要翻译： 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US20140281206A1

公开(公告)日：2014-09-18

申请号：US14132987

申请日：2013-12-18

申请人： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

发明人： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

IPC分类号： G11C11/406

CPC分类号： G11C7/02 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

摘要： Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

摘要翻译： 公开了用于概率动态随机存取存储器（DRAM）行修复的示例。 在一些示例中，使用DRAM的行敲击限制和DRAM的最大激活率可以确定概率行锤检测值。 然后可以使用概率行锤检测值，使得概率可接受地低，以致对DRAM的侵入行进行给定的激活导致在对一个或多个受害行进行相关联的执行调度的行刷新之前超过行敲击限制 与侵略者行。 其他的例子被描述和要求保护。

公开(公告)号：US20140112339A1

公开(公告)日：2014-04-24

申请号：US14060191

申请日：2013-10-22

申请人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul C. Shah ,  Sitaraman V. Iyer ,  Bill Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

发明人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul C. Shah ,  Sitaraman V. Iyer ,  Bill Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC分类号： H04L12/741

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

摘要翻译： 物理层（PHY）耦合到将包括多个通道的串行差分链路。 PHY包括发射机和接收机，以耦合到车道数量的每个车道。 耦合到每个通道的发射机被配置为将时钟嵌入到要在该通道上发送的数据，并且PHY周期性地发出阻塞链路状态（BLS）请求，以使代理进入BLS以阻止链路层飞行传输， 持续时间 PHY在从包括带内复位，进入低功率状态的进入和进入部分宽度状态的组中选择的PHY相关联任务的持续时间期间利用串行差分链路

公开(公告)号：US20140040550A1

公开(公告)日：2014-02-06

申请号：US13977603

申请日：2011-09-30

申请人： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminatan ,  Tessil Thomas ,  Taarinya Polepeddi

发明人： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminatan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC分类号： G06F12/08

CPC分类号： G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

摘要翻译： 一种包括存储器控制器电路的半导体芯片，其具有耦合到存储器通道的接口电路。 存储器控制器包括在存储器通道上实现第一存储器通道协议的第一逻辑电路。 第一存储器通道协议特定于第一易失性系统存储器技术。 接口还包括在存储器通道上实现第二存储器通道协议的第二逻辑电路。 第二存储器通道协议专用于第二非易失性系统存储器技术。 第二个存储器通道协议是事务协议。

公开(公告)号：US20100169507A1

公开(公告)日：2010-07-01

申请号：US12317896

申请日：2008-12-30

申请人： Ravi Sahita ,  David Durham ,  Arun Raghunath ,  Raj K. Ramanujan ,  Parthasarathy Sarangam

发明人： Ravi Sahita ,  David Durham ,  Arun Raghunath ,  Raj K. Ramanujan ,  Parthasarathy Sarangam

IPC分类号： G06F15/16

CPC分类号： G06F9/45558 ,  G06F2009/45595 ,  H04L63/0227 ,  H04L63/08

摘要： In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a network interface component, and a management controller. The management controller may be configured to receive information related to a subscription request for a virtual machine, generate configuration information for the network interface component based on the subscription request, and provide the configuration information to the network interface component. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，基于处理器的系统可以包括至少一个处理器，耦合到至少一个处理器的至少一个存储器，网络接口部件和管理控制器。 管理控制器可以被配置为接收关于虚拟机的订阅请求的信息，基于订阅请求生成针对网络接口组件的配置信息，并将配置信息提供给网络接口组件。 公开和要求保护其他实施例。