公开(公告)号：US07651938B2

公开(公告)日：2010-01-26

申请号：US11422795

申请日：2006-06-07

申请人： Seah Sun Too ,  Hsiang Wan Liau ,  Janet Kirkland ,  Tek Seng Tan ,  Maxat Touzelbaev ,  Raj N. Master

发明人： Seah Sun Too ,  Hsiang Wan Liau ,  Janet Kirkland ,  Tek Seng Tan ,  Maxat Touzelbaev ,  Raj N. Master

IPC分类号： H01L21/44 ,  H01L23/12

CPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/4338 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3511

摘要： Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

摘要翻译： 提供热界面材料及其在包装中的使用方法。 在一个方面，提供一种热界面材料，其包括具有第一表面和与第一表面相对的第二表面的铟预制件，内部部分和外围边界。 铟预制件具有从周边边界向内部延伸的通道。 该通道使热通量在热循环期间释放。

公开(公告)号：US07601612B1

公开(公告)日：2009-10-13

申请号：US11255971

申请日：2005-10-24

申请人： Raj N. Master ,  Junaida A. Bakar ,  Diong H. Ding ,  Srinivasan Parthasarathy

发明人： Raj N. Master ,  Junaida A. Bakar ,  Diong H. Ding ,  Srinivasan Parthasarathy

IPC分类号： H01L21/00

CPC分类号： H05K3/3436 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/3463 ,  H05K3/3494 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05599

摘要： A method for forming a solder joint for a package arrangement with a dispersed Sn microstructure provides a flip chip on a package, with a flip chip having solder bumps to be connected by eutectic solder joints to pads on the package. The eutectic solder is reflowed at a solder bump/pad interface with a eutectic reflow profile that is configured to achieve eutectic solder joints having substantially evenly distributed Sn grains. The eutectic reflow profile includes an increased cooling rate and decreased hold time with a higher peak temperature. A defined ratio of the pad openings in the solder mask to the under bump metallurgy is provided. The eutectic reflow profile and the defined ratio prolong fatigue life in the package arrangement.

摘要翻译： 用于形成具有分散的Sn微结构的封装布置的焊接接头的方法在封装上提供了倒装芯片，其中倒装芯片具有通过共晶焊点连接到封装上的焊盘的焊料凸块。 共晶焊料在具有共晶回流曲线的焊料凸块/焊盘界面处回流，其被配置为实现具有基本上均匀分布的Sn晶粒的共晶焊点。 共晶回流曲线包括增加的冷却速率和降低的保持时间，并具有较高的峰值温度。 提供了焊接掩模中的焊盘开口与凸块下金属的限定比例。 共晶回流型材和定义的比例延长了包装布置中的疲劳寿命。

公开(公告)号：US07215030B2

公开(公告)日：2007-05-08

申请号：US11167425

申请日：2005-06-27

申请人： Raj N. Master ,  Srinivasan Ashok Anand ,  Srinivasan Parthasarathy ,  Yew Cheong Mui

发明人： Raj N. Master ,  Srinivasan Ashok Anand ,  Srinivasan Parthasarathy ,  Yew Cheong Mui

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： C22C13/02 ,  B23K35/262 ,  H01L23/49811 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K3/3463 ,  H05K2201/10318 ,  H05K2201/10674 ,  H05K2203/047 ,  H01L2224/81 ,  H01L2224/0401

摘要： A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.

摘要翻译： 封装衬底包括管芯焊盘和焊脚焊脚。 针焊料焊片可以包含约90重量％至约99重量％的锡和约10重量％至1重量％的锑。 模焊盘可以包括约4重量％至约8重量％的铋，约2重量％至约4重量％的银，约0重量％至约0.7重量％的铜，以及约87重量％至约92重量％ 锡。 模焊盘可以包括约7重量％至约20重量％的铟，约2重量％至约4.5重量％的银之间，约0重量％至约0.7重量％的铜之间，约0重量％至约0.5重量％ 重量锑，以及约74.3重量％至约90重量％的锡。

公开(公告)号：US06382500B1

公开(公告)日：2002-05-07

申请号：US09642835

申请日：2000-08-22

申请人： Raj N. Master ,  Mohammad Zubair Khan ,  Maria Guardado ,  Sp Lee ,  Sofi Mohd

发明人： Raj N. Master ,  Mohammad Zubair Khan ,  Maria Guardado ,  Sp Lee ,  Sofi Mohd

IPC分类号： B23K100

CPC分类号： B23K1/203 ,  B23K1/0016 ,  B23K1/008 ,  B23K2101/40

摘要： When soldering semiconductor devices in a solder reflow furnace flux is vaporized and carried to the furnace exhaust pipe. The flux condenses on the walls of the exhaust pipe and drips back into the furnace contaminating production parts. A solder reflow furnace with a flux effluent collector prevents flux drip-back. The flux effluent collector has an exhaust gas heater that maintains flux effluent in a gaseous state, a flux cooler, to subsequently condense flux, and a flux condensation region where the flux condenses. The flux condensation region is offset from the furnace's exhaust opening so that condensed flux cannot drip back into the furnace.

摘要翻译： 当在焊料回流炉中焊接半导体器件时，助熔剂被蒸发并运送到炉排气管。 助焊剂在排气管的壁上冷凝并滴入炉中，污染生产部件。 具有助焊剂流出物收集器的焊料回流炉防止焊剂滴落。 助焊剂流出物收集器具有一个废气加热器，其保持处于气态的助熔剂流出物，助熔剂冷却器，随后冷凝助熔剂，以及通量冷凝的助熔剂冷凝区域。 助熔剂冷凝区域与炉的排气口偏离，使得冷凝的通量不能滴入炉中。

公开(公告)号：US06333253B1

公开(公告)日：2001-12-25

申请号：US09696049

申请日：2000-10-26

申请人： Terri J. Brownfield ,  Raj N. Master

发明人： Terri J. Brownfield ,  Raj N. Master

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  B23K1/203 ,  B23K3/082 ,  H01L24/11 ,  H01L24/75 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/3489

摘要： A method and apparatus are provided for selectively depositing flux on a plurality of flip-chip bumps arranged on a semiconductor by mounting a flux stamp on the semiconductor chip. The flux stamp has a plurality of flux holes arranged in a pattern substantially identically corresponding to the arrangement of the flip-chip bumps of the semiconductor chip. Different flux stamps are prepared for various kinds of semiconductor chips having different flip-chip bump arrangements. Flux is deposited though the flux holes of the flux stamp which selectively exposing the upper surfaces of the flip-chip bumps of the chip, thereby leaving no flux on the chip surface between the flip-chip bumps.

摘要翻译： 提供一种方法和装置，用于通过在半导体芯片上安装焊剂印模来选择性地在布置在半导体上的多个倒装凸块上沉积焊剂。 磁通印模具有以与半导体芯片的倒装芯片凸块的布置基本相同的形式布置的多个磁通孔。 为具有不同倒装芯片凸块布置的各种半导体芯片准备不同的磁通量戳。 焊剂通过焊剂压块的通孔沉积，其选择性地暴露芯片的倒装芯片凸块的上表面，从而在倒装芯片凸块之间的芯片表面上不留下焊剂。

公开(公告)号：US5988485A

公开(公告)日：1999-11-23

申请号：US40651

申请日：1998-03-17

申请人： Raj N. Master ,  Orion K. Starr ,  Mohammad Z. Khan

发明人： Raj N. Master ,  Orion K. Starr ,  Mohammad Z. Khan

IPC分类号： H01L21/60 ,  H01L21/48 ,  B23K1/018

CPC分类号： H01L21/4864 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701

摘要： A method of assembling a substrate and die in a flip chip configuration uses a non-hazardous cleaning solvent to clean the flux residue. The non-hazardous cleaning solvent utilized is Ionox obtained from Kyzen Corporation. Optimized process parameters are: time 10-30 minutes, temperature 70-90.degree. C., pressure 40-70 psi, rotation speed and reversals 100-1000 rpm and 24-100 reversal cycles.

摘要翻译： 以倒装芯片配置组装衬底和管芯的方法使用非危险清洁溶剂来清洁焊剂残留物。 使用的非危险清洗溶剂是从Kyzen Corporation获得的Ionox。 优化的工艺参数为：时间10-30分钟，温度70-90℃，压力40-70psi，转速和反转100-1000转和24-100反转循环。

公开(公告)号：US5553766A

公开(公告)日：1996-09-10

申请号：US342563

申请日：1994-11-21

申请人： Raymond A. Jackson ,  Kathleen A. Lidestri ,  David C. Linnell ,  Raj N. Master

发明人： Raymond A. Jackson ,  Kathleen A. Lidestri ,  David C. Linnell ,  Raj N. Master

IPC分类号： B23K1/018 ,  H05K13/04 ,  H05K3/34 ,  B23K3/00

CPC分类号： H05K13/0486 ,  B23K1/018 ,  B23K2201/40

摘要： Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.

摘要翻译： 双金属结构或记忆金属的提升环的变形与焊料软化或熔化温度匹配，以施加力以从支撑结构（例如基板或多芯片模块）提升芯片，只有当芯片之间的焊料连接 支撑结构软化或熔化。 与市售的盒式炉或带式炉等相比，芯片，模块和焊料连接的温度是可以实现的，并且与已知的热切屑去除工艺相比，在芯片内的内部芯片温度和热梯度大大降低。 与已知的冷芯片去除工艺相比，焊料连接和芯片和基板触点处的拉伸和/或剪切力大大降低。 因此，该过程可以随意重复，而不会显着损坏或改变芯片或衬底的电特性。

公开(公告)号：US5153408A

公开(公告)日：1992-10-06

申请号：US607969

申请日：1990-10-31

申请人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

发明人： Edward F. Handford ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  Raymond A. Jackson ,  Raj N. Master ,  Sudipta K. Ray ,  William E. Sablinski ,  Thomas A. Wassick

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/498 ,  H01L23/52 ,  H01L23/525 ,  H01L23/538 ,  H05K3/00 ,  H05K3/02 ,  H05K3/22 ,  H05K3/34

CPC分类号： H01L21/76892 ,  H01L23/49866 ,  H01L23/525 ,  H05K3/225 ,  H01L2924/0002 ,  H05K2201/10181 ,  H05K2201/10234 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/027 ,  H05K3/34 ,  Y10T29/49124

摘要： The present invention relates generally to a new method of repairing electrical lines, and more praticularly to repairing electrical lines having an open at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the open with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.

摘要翻译： 本发明一般涉及一种修复电线的新方法，并且更具体地涉及在装置就位时修复在模块级具有开路的电线。 使用各种方法和过程来修复电导体线中的这个开路或有缺陷的部分。 它可以通过将跨接线或熔核固定在开口处进行修复，或者可以通过沉积工艺进行修复，该沉积工艺包括但不限于用焊料型材料填充开口或插入焊料涂覆的电线并加热 焊接并允许焊料熔化并修复开路。 本发明的一个特征是在其上附着有诸如引脚，电容器等的诸如芯片和无源部件的有源部件的基板或模块上进行修复的能力。 本发明还允许修复通常不能通过常规技术修复的细线图案。

公开(公告)号：US07923850B2

公开(公告)日：2011-04-12

申请号：US12198227

申请日：2008-08-26

申请人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

发明人： Mohammad Khan ,  Jun Zhai ,  Ranjit Gannamani ,  Raj N. Master

IPC分类号： H01L23/448 ,  H01L21/56

CPC分类号： H01L23/16 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 10−6 K−1.

摘要翻译： 公开了各种半导体芯片布置及其制造方法。 一方面，提供一种制造方法，其包括将具有外周壁的半导体芯片与基板的第一侧耦合。 第一金属环耦合到衬底的第一侧。 第一金属环具有框架半导体芯片并且与外周壁隔开间隙的内周壁。 第一金属环的热膨胀系数小于约6.0×10 -6 K -1。

公开(公告)号：US20080227310A1

公开(公告)日：2008-09-18

申请号：US11687529

申请日：2007-03-16

申请人： Seah Sun Too ,  Raj N. Master ,  Jacquana Diep ,  Mohammad Khan

发明人： Seah Sun Too ,  Raj N. Master ,  Jacquana Diep ,  Mohammad Khan

IPC分类号： H01R12/00

CPC分类号： H01L23/433 ,  H01L23/467 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01R12/7076 ,  H05K7/1061 ,  H01L2224/0401

摘要： Various sockets for packaged integrated circuits and methods of making the same are provided. In one aspect, a method of mounting a semiconductor chip is provided that includes providing a package that has a base substrate with a first side and a second side opposite the first side. The second side has a central region. The package includes a semiconductor chip and a lid coupled to the first side. A socket is provided for receiving the base substrate. The socket includes a mound that projects toward the second side of the base substrate when the base substrate is seated in the socket to provide support for the central region of the base substrate. The package is mounted in the socket. The mound provides support for the central region of the base substrate.

摘要翻译： 提供了用于封装集成电路的各种插座及其制造方法。 一方面，提供了一种安装半导体芯片的方法，其包括提供具有第一侧和与第一侧相对的第二侧的基底的封装。 第二边有一个中部地区。 该封装包括半导体芯片和连接到第一侧的盖子。 提供了用于接收基底的插座。 插座包括当基底座位于插座中时朝向基底基板的第二侧突出的墩，以为基底基板的中心区域提供支撑。 包装安装在插座中。 土丘为基底的中心区域提供支撑。