公开(公告)号：US20120181549A1

公开(公告)日：2012-07-19

申请号：US13009029

申请日：2011-01-19

Applicant: Jeffrey B. Johnson ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus ,  Kai Xiu

Inventor： Jeffrey B. Johnson ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus ,  Kai Xiu

IPC: H01L29/161 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Abstract translation: 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。

公开(公告)号：US07932189B2

公开(公告)日：2011-04-26

申请号：US11627817

申请日：2007-01-26

Applicant: Tushar P. Merchant ,  Chun-Li Liu ,  Ramachandran Muralidhar ,  Marius K. Orlowski ,  Rajesh A. Rao ,  Matthew Stoker

Inventor： Tushar P. Merchant ,  Chun-Li Liu ,  Ramachandran Muralidhar ,  Marius K. Orlowski ,  Rajesh A. Rao ,  Matthew Stoker

IPC: H01L21/31

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/11524 ,  H01L29/7887 ,  Y10S977/932 ,  Y10S977/943

Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

Abstract translation: 电子设备可以包括不连续的存储元件层。 覆盖不连续存储元件的电介质层可以是基本上无氢的。 形成电子器件的工艺可以包括在不连续的存储元件上形成包括硅的层。 在一个实施方案中，该方法包括至少基本上氧化所有该层。 在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成层并至少基本上全部氧化。

公开(公告)号：US20090085024A1

公开(公告)日：2009-04-02

申请号：US11864246

申请日：2007-09-28

Applicant: Ramachandran Muralidhar ,  Tushar P. Merchant ,  Rajesh A. Rao

Inventor： Ramachandran Muralidhar ,  Tushar P. Merchant ,  Rajesh A. Rao

IPC: H01L47/00 ,  B05D5/12

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

Abstract: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.

Abstract translation: 相变存储单元具有第一电极，多个柱和第二电极。 多个柱与第一电极电耦合。 每个支柱包括相变材料部分和加热器材料部分。 第二电极电耦合到每个支柱。 在一些示例中，支柱具有小于20纳米的宽度。

公开(公告)号：US07432158B1

公开(公告)日：2008-10-07

申请号：US11459843

申请日：2006-07-25

Applicant: Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

Inventor： Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/36

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S977/774 ,  Y10S977/779 ,  Y10S977/78 ,  Y10S977/943

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract translation: 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 第一介电层形成在半导体层上。 在第一部分上形成第一多个纳米团簇，并且在第二部分上形成第二多个纳米团簇。 在第一多个和第二多个纳米团簇的每个纳米簇周围形成氮化氧化物层。 在第一多个纳米团簇的氮化氧化物层上进行远程等离子体氮化。 从第二部分去除纳米团簇。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。

公开(公告)号：US20080199996A1

公开(公告)日：2008-08-21

申请号：US11676403

申请日：2007-02-19

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

Abstract translation: 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中在牺牲隔离物上形成的纳米团簇被去除并且其它纳米团簇保留。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

公开(公告)号：US20080188052A1

公开(公告)日：2008-08-07

申请号：US11671809

申请日：2007-02-06

Applicant: Brian A. Winstead ,  Taras A. Kirichenko ,  Konstantin V. Loiko ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sung-Taeg Kang ,  Ko-Min Chang ,  Jane Yater

Inventor： Brian A. Winstead ,  Taras A. Kirichenko ,  Konstantin V. Loiko ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sung-Taeg Kang ,  Ko-Min Chang ,  Jane Yater

IPC: H01L21/336

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).

Abstract translation: 公开了一种半导体工艺和装置，用于通过在衬底（1）上的第一介电层（2）上形成选择栅极结构（3）来形成分裂栅极薄膜存储NVM器件（10）。 在具有嵌入的纳米晶体（15,16）的第二介电层（5）上形成控制栅极结构（6），使得所述控制栅极（6）与所述选择栅极结构（3）相邻，但是通过间隙（8 ）; 在形成在选择栅极结构和控制栅极结构之间的间隙（8）下面的衬底（1）中形成浮置掺杂区（4）; 以及在所述衬底中形成源/漏区（11,12）以限定包括所述浮置掺杂区（4）的沟道区。

公开(公告)号：US20080182428A1

公开(公告)日：2008-07-31

申请号：US11627817

申请日：2007-01-26

Applicant: Tushar P. Merchant ,  Chun-Li Liu ,  Ramachandran Muralidhar ,  Marius K. Orlowski ,  Rajesh A. Rao ,  Matthew Stoker

Inventor： Tushar P. Merchant ,  Chun-Li Liu ,  Ramachandran Muralidhar ,  Marius K. Orlowski ,  Rajesh A. Rao ,  Matthew Stoker

IPC: H01L21/31

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L27/11524 ,  H01L29/7887 ,  Y10S977/932 ,  Y10S977/943

Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.

Abstract translation: 电子设备可以包括不连续的存储元件层。 覆盖不连续存储元件的电介质层可以是基本上无氢的。 形成电子器件的过程可以包括在不连续的存储元件上形成包括硅的层。 在一个实施方案中，该方法包括至少基本上氧化所有该层。 在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成该层并至少基本上全部氧化。

公开(公告)号：US20080182377A1

公开(公告)日：2008-07-31

申请号：US11668210

申请日：2007-01-29

Applicant: Rajesh A. Rao ,  Ramachandran Muralidhar

Inventor： Rajesh A. Rao ,  Ramachandran Muralidhar

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/66772 ,  H01L29/7887

Abstract: In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.

Abstract translation: 在制造多位存储单元时，在半导体衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 一层栅极材料形成在第二绝缘层之上并图案化以留下栅极部分。 蚀刻第二绝缘层以切割栅极部分，并将第二绝缘层的一部分留在第一绝缘层和栅极部分之间。 在第一绝缘层上形成纳米晶体。 纳米晶体的第一部分在第二绝缘层部分的第一侧上的栅极部分下方，并且纳米晶体的第二部分在第二绝缘层部分的第二侧上的栅极部分下方。 纳米晶体的第一和第二部分分别用于存储第一和第二位的逻辑状态。

公开(公告)号：US20080121966A1

公开(公告)日：2008-05-29

申请号：US11530053

申请日：2006-09-08

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/773

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

公开(公告)号：US07098502B2

公开(公告)日：2006-08-29

申请号：US10705317

申请日：2003-11-10

Applicant: Leo Mathew ,  Ramachandran Muralidhar

Inventor： Leo Mathew ,  Ramachandran Muralidhar

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/00 ,  H01L21/336

CPC classification number: H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Abstract translation: 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。