公开(公告)号：US20130154026A1

公开(公告)日：2013-06-20

申请号：US13330817

申请日：2011-12-20

Applicant: Emre Alptekin ,  Reinaldo Vega

Inventor： Emre Alptekin ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/768

CPC classification number: H01L29/665 ,  H01L21/28525 ,  H01L21/76804 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

Abstract translation: 本发明的实施例提供一种用于晶体管的接触结构。 接触结构包括分别在第一和第二晶体管的第一和第二栅极之间的第一外延生长区域; 第二外延生长区域直接在第一外延生长区域的顶部上，第二外延生长区域的宽度比第一外延生长区域的宽度宽; 以及形成在所述第二外延生长区域的顶部上的硅化物区域，其中所述硅化物区域具有与所述第一外延生长区域相比更接近所述第二外延生长区域的其余部分的界面。 在一个实施例中，第二外延生长区域处于第一和第二晶体管的第一和第二栅极的顶表面上方的水平。

公开(公告)号：US07548455B2

公开(公告)日：2009-06-16

申请号：US11745328

申请日：2007-05-07

Applicant: Reinaldo Vega ,  Stephen Sudirgo

Inventor： Reinaldo Vega ,  Stephen Sudirgo

IPC: G11C11/36

CPC classification number: G11C11/412 ,  G11C11/38 ,  G11C11/5692

Abstract: A memory cell and method for making a memory cell in accordance with embodiments of the present invention includes two or more tunnel diodes, a loading system, and a driving system. The two or more tunnel diodes are coupled together, the loading system is coupled to the tunnel diodes and the driving system is coupled to the tunnel diodes and the loading system. The driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states.

Abstract translation: 根据本发明的实施例的用于制造存储单元的存储单元和方法包括两个或更多个隧道二极管，负载系统和驱动系统。 两个或更多个隧道二极管耦合在一起，负载系统耦合到隧道二极管，并且驱动系统耦合到隧道二极管和负载系统。 驱动系统在至少三个或更多基本稳定的逻辑状态之间从隧道二极管，负载系统和驱动系统驱动感测节点。

公开(公告)号：US20080037316A1

公开(公告)日：2008-02-14

申请号：US11745328

申请日：2007-05-07

Applicant: Reinaldo Vega ,  Stephen Sudirgo

Inventor： Reinaldo Vega ,  Stephen Sudirgo

IPC: G11C11/00 ,  G11C11/36 ,  H01L21/8234

CPC classification number: G11C11/412 ,  G11C11/38 ,  G11C11/5692

Abstract: A memory cell and method for making a memory cell in accordance with embodiments of the present invention includes two or more tunnel diodes, a loading system, and a driving system. The two or more tunnel diodes are coupled together, the loading system is coupled to the tunnel diodes and the driving system is coupled to the tunnel diodes and the loading system. The driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states.

Abstract translation: 根据本发明的实施例的用于制造存储单元的存储单元和方法包括两个或更多个隧道二极管，负载系统和驱动系统。 两个或更多个隧道二极管耦合在一起，负载系统耦合到隧道二极管，并且驱动系统耦合到隧道二极管和负载系统。 驱动系统在至少三个或更多基本稳定的逻辑状态之间从隧道二极管，负载系统和驱动系统驱动感测节点。

公开(公告)号：US08853862B2

公开(公告)日：2014-10-07

申请号：US13330817

申请日：2011-12-20

Applicant: Emre Alptekin ,  Reinaldo Vega

Inventor： Emre Alptekin ,  Reinaldo Vega

IPC: H01L21/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/311

CPC classification number: H01L29/665 ,  H01L21/28525 ,  H01L21/76804 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

Abstract translation: 本发明的实施例提供一种用于晶体管的接触结构。 接触结构包括分别在第一和第二晶体管的第一和第二栅极之间的第一外延生长区域; 第二外延生长区域直接在第一外延生长区域的顶部上，第二外延生长区域的宽度比第一外延生长区域的宽度宽; 以及形成在所述第二外延生长区域的顶部上的硅化物区域，其中所述硅化物区域具有与所述第一外延生长区域相比更接近所述第二外延生长区域的其余部分的界面。 在一个实施例中，第二外延生长区域处于第一和第二晶体管的第一和第二栅极的顶表面上方的水平。