公开(公告)号：US20110038127A1

公开(公告)日：2011-02-17

申请号：US12907023

申请日：2010-10-18

Applicant: Rey BRUCE ,  Ricardo Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

Inventor： Rey BRUCE ,  Ricardo Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

IPC: H01L25/07 ,  H01L21/50

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/15331 ,  H01L2924/1627

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。

公开(公告)号：US20070158808A1

公开(公告)日：2007-07-12

申请号：US11322442

申请日：2005-12-29

Applicant: Rey Bruce ,  Ricardo Bruce ,  Patrick Bugayong ,  Joel Baylon

Inventor： Rey Bruce ,  Ricardo Bruce ,  Patrick Bugayong ,  Joel Baylon

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/15331 ,  H01L2924/1627

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. Combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 这些模块和裸片在基板中的组合产生具有特定功能或一定范围的存储容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。

公开(公告)号：US07620748B1

公开(公告)日：2009-11-17

申请号：US11399736

申请日：2006-04-06

Applicant: Ricardo Bruce ,  Rey Bruce ,  Federico Zalzos Sambilay, Jr. ,  Bernard Sherwin Leung Chiw

Inventor： Ricardo Bruce ,  Rey Bruce ,  Federico Zalzos Sambilay, Jr. ,  Bernard Sherwin Leung Chiw

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.

Abstract translation: 在传统的存储设备系统中，从存储器到IO总线的数据传输必须经过中间的易失性存储器（cache）。 因此，数据传输在两个步骤中完成 - 数据从存储器传输到缓存，然后从缓存传输到IO总线。 内存到高速缓存传输由一个DMA引擎和另一个DMA引擎来处理，用于缓存到IO传输。 为了开始传输，处理器准备从存储器到缓存的DMA传输。 在内存到高速缓存传输完成后，处理器被中断以准备从缓存到IO的传输。 在传输之间，处理器必须介入以利用宝贵的处理器周期设置下一个传输。 本发明使用两种新颖的方案改进了上述过程; 1）使用依赖关系表，以便从处理器的干预更少，从内存到IO的传输，以及2）使用总线侦听方案绕过传输缓存，从而将传输直接从内存传输到IO总线。 这使得从内存到IO的传输在单次传输中完成。

公开(公告)号：US07826243B2

公开(公告)日：2010-11-02

申请号：US11322442

申请日：2005-12-29

Applicant: Rey Bruce ,  Ricardo Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

Inventor： Rey Bruce ,  Ricardo Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

IPC: G11C5/02

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/15331 ,  H01L2924/1627

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。