公开(公告)号：US20060294487A1

公开(公告)日：2006-12-28

申请号：US11159915

申请日：2005-06-23

申请人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

发明人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  G06F17/5077 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

摘要翻译： 一种用于在半导体器件的第一I / O端子与载体的第二I / O端子之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的每个第一因素的多个第一因素和实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 每个第一因子的实例与每个相关联的第二因子的实例在一对一的基础上相关。 在每个第一I / O终端和匹配的第二I / O终端之间自动生成模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与相关联的第二因素的识别实例相关联 的匹配第二个I / O端子。

公开(公告)号：US20050278667A1

公开(公告)日：2005-12-15

申请号：US11160266

申请日：2005-06-16

申请人： Matt Boucher ,  John Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith McCullen ,  Sarah Braasch ,  Michael Sitko

发明人： Matt Boucher ,  John Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith McCullen ,  Sarah Braasch ,  Michael Sitko

IPC分类号： G01R31/303 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/3025 ,  G01R31/303

摘要： The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

摘要翻译： 本发明提供了用于诊断集成电路的方法，系统和程序产品。 特别地，本发明为集成电路的每个相关电路层捕获一个或多个图像。 基于图像，生成组件网表。 此外，通过将分层组合规则应用于组件网表生成逻辑网表。 组件网表和/或逻辑网表可以与参考网表进行比较以诊断集成电路。 本发明还可以根据从网表确定的端口，功率和/或组件引脚连接信息，组件网络表或逻辑网表，其中组件被布置。 此外，可以以选择性地显示布线连接以辅助用户智能地布置电路部件的方式来显示原理图。

公开(公告)号：US20080010625A1

公开(公告)日：2008-01-10

申请号：US11858995

申请日：2007-09-21

申请人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

发明人： Adam Bittner ,  Timothy Budell ,  Robert Cusimano ,  Richard Dauphin ,  Matthew Guzowski ,  Craig Lussier ,  David Stone ,  Patrick Wilder

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  G06F17/5077 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in said second region.

摘要翻译： 一种用于在半导体器件和载体之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的多个第一因子和每个第一因素的实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 在第一I / O端子和匹配的第二I / O端子之间产生模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与所识别的相关联的第二因子的实例相关联 匹配的第二个I / O终端。 在位于第一区域的第三I / O端子和位于所述第二区域中的第四I / O端子之间产生模拟布线连接。

公开(公告)号：US07503021B2

公开(公告)日：2009-03-10

申请号：US11160266

申请日：2005-06-16

申请人： Matt Boucher ,  John M. Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith H. McCullen ,  Sarah C. Braasch ,  Michael H. Sitko

发明人： Matt Boucher ,  John M. Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith H. McCullen ,  Sarah C. Braasch ,  Michael H. Sitko

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/3025 ,  G01R31/303

摘要： The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

摘要翻译： 本发明提供了用于诊断集成电路的方法，系统和程序产品。 特别地，本发明为集成电路的每个相关电路层捕获一个或多个图像。 基于图像，生成组件网表。 此外，通过将分层组合规则应用于组件网表生成逻辑网表。 组件网表和/或逻辑网表可以与参考网表进行比较以诊断集成电路。 本发明还可以根据从网表确定的端口，功率和/或组件引脚连接信息，组件网络表或逻辑网表，其中组件被布置。 此外，可以以选择性地显示布线连接以辅助用户智能地布置电路部件的方式来显示原理图。

公开(公告)号：US07275229B2

公开(公告)日：2007-09-25

申请号：US11159915

申请日：2005-06-23

申请人： Adam Matthew Bittner ,  Timothy W. Budell ,  Robert C. Cusimano ,  Richard Dauphin ,  Matthew Thomas Guzowski ,  Craig Paul Lussier ,  David Brian Stone ,  Patrick G. Wilder

发明人： Adam Matthew Bittner ,  Timothy W. Budell ,  Robert C. Cusimano ,  Richard Dauphin ,  Matthew Thomas Guzowski ,  Craig Paul Lussier ,  David Brian Stone ,  Patrick G. Wilder

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  G06F17/5077 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

摘要翻译： 一种用于在半导体器件的第一I / O端子与载体的第二I / O端子之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的每个第一因素的多个第一因素和实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 每个第一因子的实例与每个相关联的第二因子的实例在一对一的基础上相关。 在每个第一I / O终端和匹配的第二I / O终端之间自动生成模拟接线连接，受到每个第一I / O端子的每个第一因子的识别实例与相关联的第二因素的识别实例相关联 的匹配第二个I / O端子。

公开(公告)号：US07765509B2

公开(公告)日：2010-07-27

申请号：US11858995

申请日：2007-09-21

申请人： Adam Matthew Bittner ,  Timothy W. Budell ,  Robert C. Cusimano ,  Richard Dauphin ,  Matthew Thomas Guzowski ,  Craig Paul Lussier ,  David Brian Stone ,  Patrick G. Wilder

发明人： Adam Matthew Bittner ,  Timothy W. Budell ,  Robert C. Cusimano ,  Richard Dauphin ,  Matthew Thomas Guzowski ,  Craig Paul Lussier ,  David Brian Stone ,  Patrick G. Wilder

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  G06F17/5077 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in a second region.

摘要翻译： 一种用于在半导体器件和载体之间产生模拟布线连接的系统和方法。 该方法包括识别与半导体器件相关的多个第一因子和每个第一因素的实例，并且识别与载波相关的每个第二因素的多个第二因素和实例。 第一和第二因素在一对一的基础上相互关联。 在第一I / O端子和匹配的第二I / O端子之间产生模拟的布线连接，受到每个第一I / O端子的每个第一因子的识别的实例与所识别的相关联的第二因子的实例相关联 匹配的第二个I / O终端。 在位于第一区域的第三I / O端子和位于第二区域中的第四I / O端子之间产生模拟布线连接。