公开(公告)号：US09016236B2

公开(公告)日：2015-04-28

申请号：US12185339

申请日：2008-08-04

申请人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

发明人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

IPC分类号： H01L21/306 ,  C23C16/00 ,  C23C16/507 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  C23C16/458 ,  C23C16/56 ,  H01J37/20 ,  H01J37/32 ,  H01L27/108 ,  H01L21/316 ,  H01L21/318

CPC分类号： C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

摘要： A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an “electron filter” that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.

摘要翻译： 公开了一种高密度等离子体化学气相沉积工具和该工具的使用方法。 化学气相沉积工具允许对保持正在制造的衬底的基座进行角度调节。 电磁铁用作允许将材料角度沉积到衬底上的“电子过滤器”。 还公开了在半导体制造工艺中制造沟槽结构和不对称间隔物的方法。 角度沉积节省了工艺步骤，从而降低了制造时间，复杂性和成本，同时提高了整体产品的产量。

公开(公告)号：US08507375B1

公开(公告)日：2013-08-13

申请号：US13364976

申请日：2012-02-02

申请人： André P. Labonté ,  Richard S. Wise

发明人： André P. Labonté ,  Richard S. Wise

IPC分类号： H01L21/44

CPC分类号： H01L21/28247 ,  H01L21/76814 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/66545

摘要： An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.

摘要翻译： 通过提供其上具有上表面的第一导电区域（例如，MOSFET栅极）的衬底来形成对准容限的电接触，所述第一导电区域被第一介电区域横向界定，施加具有 部分地覆盖在衬底上并在上表面的一部分上的接触区域（例如，用于MOSFET源极或漏极）上的开口，形成通过延伸到接触区域和上表面的部分的第一介电区域的通道， 从而暴露接触区域和上表面的一部分，将上表面的一部分转换成第二电介质区域，并且用与接触区域电接触但与导电区域电绝缘的导体填充开口 电介质区域。

公开(公告)号：US20120306093A1

公开(公告)日：2012-12-06

申请号：US13151646

申请日：2011-06-02

申请人： Brett H. Engel ,  Ying Li ,  Viraj Y. Sardesai ,  Richard S. Wise

发明人： Brett H. Engel ,  Ying Li ,  Viraj Y. Sardesai ,  Richard S. Wise

IPC分类号： H01L21/283 ,  H01L23/48 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L21/31144 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76829

摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.

摘要翻译： 一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。 半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

公开(公告)号：US08193099B1

公开(公告)日：2012-06-05

申请号：US13049933

申请日：2011-03-17

申请人： Mukesh V. Khare ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Richard S. Wise ,  Hongwen Yan

发明人： Mukesh V. Khare ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Richard S. Wise ,  Hongwen Yan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32136 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878

摘要： A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.

摘要翻译： 形成半导体器件的方法包括在具有有源区和浅沟槽隔离（STI）区的衬底上形成晶体管栅叠。 第一侧壁间隔物形成在晶体管栅极堆叠上，并且各向同性蚀刻工艺被应用于各向同性地去除包括在晶体管栅极叠层内的金属层的过剩部分，剩余部分未被第一侧壁间隔物保护。 第二侧壁间隔物形成在晶体管栅极叠层上，第二侧壁间隔物完全封装晶体管栅极叠层的金属层。

公开(公告)号：US07498271B1

公开(公告)日：2009-03-03

申请号：US12145035

申请日：2008-06-24

申请人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

发明人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

IPC分类号： H01L21/31

CPC分类号： H01L21/31138 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

摘要翻译： 本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体 材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。

公开(公告)号：US06838347B1

公开(公告)日：2005-01-04

申请号：US10605331

申请日：2003-09-23

申请人： Joyce C. Liu ,  Wesley C. Natzle ,  Richard S. Wise ,  Hongwen Yan ,  Bidan Zhang

发明人： Joyce C. Liu ,  Wesley C. Natzle ,  Richard S. Wise ,  Hongwen Yan ,  Bidan Zhang

IPC分类号： H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/31116

摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

公开(公告)号：US06656375B1

公开(公告)日：2003-12-02

申请号：US09014806

申请日：1998-01-28

申请人： Michael D. Armacost ,  David M. Dobuzinsky ,  John C. Malinowski ,  Hung Y. Ng ,  Richard S. Wise ,  Chienfan Yu

发明人： Michael D. Armacost ,  David M. Dobuzinsky ,  John C. Malinowski ,  Hung Y. Ng ,  Richard S. Wise ,  Chienfan Yu

IPC分类号： C23F100

CPC分类号： H01L21/31116

摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.

摘要翻译： 用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。 富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。 氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。

公开(公告)号：US06355567B1

公开(公告)日：2002-03-12

申请号：US09345646

申请日：1999-06-30

申请人： Scott D. Halle ,  Paul C. Jamison ,  David E. Kotecki ,  Richard S. Wise

发明人： Scott D. Halle ,  Paul C. Jamison ,  David E. Kotecki ,  Richard S. Wise

IPC分类号： H01L21311

CPC分类号： H01L21/76879 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/7682 ,  H01L21/76885

摘要： Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.

摘要翻译： 薄膜中的逆行开口及其形成方法。 开口可以包括形成在开口内的导电材料，以用作包括具有锥形横截面的导线的布线图案。 该方法涉及用于在膜内形成具有影响所选择的蚀刻剂物质的蚀刻速率的特性梯度的逆向开口的两步蚀刻方法。 首先通过各向异性蚀刻工艺在膜内形成开口。 然后通过对特性有选择性的各向同性蚀刻工艺将开口转换成包括逆行特征的开口。 此后，逆行开口填充有导电材料，在一种情况下，通过电镀或其它沉积技术。

公开(公告)号：US6093281A

公开(公告)日：2000-07-25

申请号：US31232

申请日：1998-02-26

申请人： Richard S. Wise ,  David M. Dobuzinsky ,  William C. Wille

发明人： Richard S. Wise ,  David M. Dobuzinsky ,  William C. Wille

IPC分类号： C23C16/44 ,  H01J37/32 ,  C23C16/00

CPC分类号： H01J37/32834 ,  C23C16/4412 ,  H01J37/3244

摘要： A baffle plate for semiconductor processing apparatus. The baffle plate includes a plurality of slits. A plurality of fins are located between adjacent slits. The fins have varying heights and a supporting portion interconnects the fins.

摘要翻译： 一种用于半导体处理装置的挡板。 挡板包括多个狭缝。 多个翅片位于相邻狭缝之间。 翅片具有不同的高度，并且支撑部分互连翅片。

公开(公告)号：US08901006B2

公开(公告)日：2014-12-02

申请号：US13081020

申请日：2011-04-06

申请人： Xiang Hu ,  Richard S. Wise ,  Habib Hichri ,  Catherine Labelle

发明人： Xiang Hu ,  Richard S. Wise ,  Habib Hichri ,  Catherine Labelle

IPC分类号： H01L21/3213 ,  H01L21/311 ,  H01L27/11 ,  H01L21/3105

CPC分类号： H01L23/48 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/3213 ,  H01L21/32139 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

摘要翻译： 在图案转印和后续短路过程中的抗反射残余物通过使用下面的牺牲层来确保完全去除抗反射层而消除。 实施例包括在导电层（例如硅衬底）上形成硬掩模层，在硬掩模层上形成牺牲层，在牺牲层上形成光学色散层，在光学色散上形成硅抗反射涂层 在硅抗反射涂层上形成光致抗蚀剂层，其中光致抗蚀剂层限定图案，蚀刻以将图案转移到硬掩模层，以及剥离至少光学色散层和牺牲层。