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1.发明授权Wide frequency range signal generator and method, and integrated circuit test system using same 有权宽频率范围信号发生器及方法，集成电路测试系统采用相同方式公开(公告)号：US07536618B2
公开(公告)日：2009-05-19
申请号：US11442515
申请日：2006-05-25
Applicant: Greg Rausch , Rob Rabe , Jake Klier
Inventor： Greg Rausch , Rob Rabe , Jake Klier
IPC: G01R31/28
CPC classification number: G01R31/31922 , G06F1/08 , G11C29/56 , G11C29/56012 , H03K23/002
Abstract: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.
Abstract translation: 信号发生器通过将输入时钟信号通过多个分频器电路产生输出时钟信号，每个分频器电路由触发触发器形成。 通过选择耦合输入时钟信号的触发器来调整输出时钟信号的频率。 重定时器触发器可以耦合在相邻的翻转翻转之间，以重新同步通过触发器耦合的信号。 每个重定时器触发器在其数据输入处从上游触发器的输出接收相应的信号，并且在其时钟输入端接收输入时钟信号。 然后触发器与输入时钟信号同步地将信号施加到下游触发器。 输入信号耦合的最后两个触发器可以预设为各种状态，以将输出时钟信号的相位设置为四相中的一个。
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2.发明申请Wide frequency range signal generator and method, and integrated circuit test system using same 有权宽频率范围信号发生器及方法，集成电路测试系统采用相同方式
公开(公告)号：US20070300111A1
公开(公告)日：2007-12-27
申请号：US11442515
申请日：2006-05-25
Applicant: Greg Rausch , Rob Rabe , Jake Klier
Inventor： Greg Rausch , Rob Rabe , Jake Klier
IPC: G01R31/28
CPC classification number: G01R31/31922 , G06F1/08 , G11C29/56 , G11C29/56012 , H03K23/002
Abstract: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.
Abstract translation: 信号发生器通过将输入时钟信号通过多个分频器电路产生输出时钟信号，每个分频器电路由触发触发器形成。 通过选择耦合输入时钟信号的触发器来调整输出时钟信号的频率。 重定时器触发器可以耦合在相邻的翻转翻转之间，以重新同步通过触发器耦合的信号。 每个重定时器触发器在其数据输入处从上游触发器的输出接收相应的信号，并且在其时钟输入端接收输入时钟信号。 然后触发器与输入时钟信号同步地将信号施加到下游触发器。 输入信号耦合的最后两个触发器可以预设为各种状态，以将输出时钟信号的相位设置为四相中的一个。
