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    STI punch-through defects and stress reduction by high temperature oxide reflow process
    1.
    发明授权
    STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
    STI穿透缺陷和通过高温氧化物回流工艺的应力降低

    公开(公告)号：US06309942B1

    公开(公告)日：2001-10-30

    申请号：US09245161

    申请日：1999-02-04

    Applicant: Ting Y. Tsui ,  Robert H. Tu ,  Xiao-Yu Li ,  Sunil D. Mehta

    Inventor： Ting Y. Tsui ,  Robert H. Tu ,  Xiao-Yu Li ,  Sunil D. Mehta

    IPC: H01L2176

    CPC classification number: H01L21/76229

    Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.

    Abstract translation: 公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。 所公开的方法开始于提供包括封盖层的硅衬底。 然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。 然后用氧化物层填充隔离沟槽。 然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。 在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

    Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb
    2.
    发明授权
    Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb 有权
    操作具有具有薄栅极氧化物和减少干扰的晶体管的EEPROM存储单元的方法

    公开(公告)号：US06208559B1

    公开(公告)日：2001-03-27

    申请号：US09441220

    申请日：1999-11-15

    Applicant: Robert H. Tu ,  Sunil D. Mehta

    Inventor： Robert H. Tu ,  Sunil D. Mehta

    IPC: G11C1604

    CPC classification number: G11C16/3427 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/115

    Abstract: An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.

    Abstract translation: 编程和擦除相同单元阵列中的EEPROM存储单元的改进过程使用待编程或擦除的单元写入晶体管上的降低的电压，同时在写入晶体管的相对薄的氧化物上施加较小的电压 的阵列中的其他电池，以便减少这些电池中的氧化物泄漏和损坏，但是不会干扰存储在这些电池中的信息。 结果是能够缩小EEPROM存储单元的尺寸，从而增强经济性，并允许更快的编程，擦除和读取速度。

    Reduction of mechanical stress in shallow trench isolation process
    4.
    发明授权
    Reduction of mechanical stress in shallow trench isolation process 有权
    浅沟槽隔离过程中机械应力的降低

    公开(公告)号：US06221733B1

    公开(公告)日：2001-04-24

    申请号：US09192096

    申请日：1998-11-13

    Applicant: Xiao-Yu Li ,  Sunil D. Mehta ,  Robert H. Tu

    Inventor： Xiao-Yu Li ,  Sunil D. Mehta ,  Robert H. Tu

    IPC: H01L2176

    CPC classification number: H01L21/76232 ,  Y10S148/05

    Abstract: A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

    Abstract translation: 提供了一种使标准浅沟槽隔离（STI）工艺中的沟槽形成/沟槽填充工艺步骤期间产生的机械应力最小化的方法。 这是通过形成具有更倾斜和更平滑轮廓的沟槽和/或限制沟槽深度小于0.4μm，和/或减小或增加沟槽致密化温度，和/或在化学处理之后执行致密化步骤来实现的， 机械抛光步骤。 此外，使用炉TEOS氧化物膜作为沟槽填充材料。

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