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公开(公告)号：US08753917B2
公开(公告)日：2014-06-17
申请号：US12967625
申请日：2010-12-14
IPC分类号： H01L31/112
CPC分类号： H01L31/105 , H01L27/14632 , H01L27/14636 , H01L27/14665 , H01L27/14687
摘要： A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括设置在中间层上的第一介电层，设置在第一介电层上的第一导电焊盘部分和第一互连部分，设置在第一介电层上的第二介电层 电介质层，设置在第一互连部分上的第一覆盖层和第一导电焊盘部分的一部分，设置在第一覆盖层上的第二封盖层和第二介电层的一部分，设置n型掺杂硅层 在第二覆盖层和第一导电焊盘部分上，设置在n型掺杂硅层上的本征硅层和设置在本征硅层上的p型掺杂硅层。
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2.发明授权Resized wafer with a negative photoresist ring and design structures thereof 有权具有负光致抗蚀剂环的尺寸调整晶片及其设计结构公开(公告)号：US08536025B2
公开(公告)日：2013-09-17
申请号：US13316978
申请日：2011-12-12
IPC分类号： H01L21/46 , H01L21/301
CPC分类号： H01L21/76838 , H01L21/302 , H01L21/3083
摘要： A resized wafer using a negative photoresist ring, methods of manufacture and design structures thereof are disclosed. The method includes forming a ring within a radius of a wafer. The method also includes patterning a photoresist formed on the wafer, by exposing the photoresist to energy. Additionally, the method includes forming troughs in a substrate of the wafer based on the patterning of the photoresist, wherein the ring blocks formation of the troughs underneath the ring. The method also includes filling the troughs with a metal and resizing the wafer at an area of the ring.
摘要翻译： 公开了使用负型光致抗蚀剂环的尺寸调整的晶片，其制造方法和设计结构。 该方法包括在晶片的半径内形成环。 该方法还包括通过将光致抗蚀剂暴露于能量来图案化形成在晶片上的光致抗蚀剂。 另外，该方法包括基于光刻胶的图案形成在晶片的衬底中形成槽，其中环阻挡环下方的槽的形成。 该方法还包括用金属填充槽并且在环的区域上调整晶片大小。
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3.发明授权Apparatus for real-time contamination, environmental, or physical monitoring of a photomask 有权用于光掩模的实时污染，环境或物理监测的装置公开(公告)号：US07929117B2
公开(公告)日：2011-04-19
申请号：US12056047
申请日：2008-03-26
CPC分类号： G03F1/84 , G03F7/7085 , G03F7/70875 , G03F7/709 , G03F7/70916 , G03F7/70983
摘要： An apparatus for real-time contamination, environmental, or physical monitoring of a photomask. The apparatus includes a photomask having a patterned region configured to correspond to features of an integrated circuit and a sensor physically coupled with the photomask. The sensor is configured to monitor an attribute related to the photomask. Attributes monitored by the sensor may include chemical contamination, temperature changes, humidity changes, acceleration, shock, vibration, optical flux through the photomask, electrostatic discharge environment of the photomask, particulates, and pressure.
摘要翻译： 一种用于光掩模的实时污染，环境或物理监测的设备。 该装置包括光掩模，其具有被配置为对应于集成电路的特征的图案区域和与光掩模物理耦合的传感器。 传感器被配置为监视与光掩模相关的属性。 由传感器监测的属性可能包括化学污染，温度变化，湿度变化，加速度，冲击，振动，通过光掩模的光通量，光掩模的静电放电环境，微粒和压力。
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公开(公告)号：US07707535B2
公开(公告)日：2010-04-27
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译： 公开了拼接集成电路（IC）芯片布局设计结构。 在一个实施例中，在设计过程中使用的机器可读介质中体现的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片布局，所述IC芯片布局包括：多个缝合区域， 至少一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。
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5.发明申请公开(公告)号：US20100031223A1
公开(公告)日：2010-02-04
申请号：US12182672
申请日：2008-07-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70916 , G03F7/70525 , G03F7/70741 , G03F7/7085 , G03F7/70991
摘要： Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device.
摘要翻译： 用于光掩模的实时污染，环境或物理监测的系统。 该系统包括物理地安装到光掩模的电子封装以及与电子封装通信的处理装置。 电子组件包括配置成监视属性并生成传感器数据的传感器。 处理装置被配置为分析从电子包装传送到处理装置的传感器数据。
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公开(公告)号：US20090302406A1
公开(公告)日：2009-12-10
申请号：US12132875
申请日：2008-06-04
CPC分类号： H01L27/14627 , H01L27/1463 , H01L27/14632 , H01L27/14636
摘要： A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.
摘要翻译： 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。
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7.发明申请STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT 有权针对IC芯片布局布线的电路区域边界标注公开(公告)号：US20090276748A1
公开(公告)日：2009-11-05
申请号：US12112329
申请日：2008-04-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。
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公开(公告)号：US20090124047A1
公开(公告)日：2009-05-14
申请号：US12353549
申请日：2009-01-14
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L21/70
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。
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公开(公告)号：US20080088014A1
公开(公告)日：2008-04-17
申请号：US11528227
申请日：2006-09-26
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。
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公开(公告)号：US07193289B2
公开(公告)日：2007-03-20
申请号：US10904807
申请日：2004-11-30
IPC分类号： H01L27/14
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： 一种图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。
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