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    Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure
    2.
    发明授权
    Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure 有权
    具有P型硅锗或硅碳化硅栅的结型场效应晶体管结构和形成该结构的方法

    公开(公告)号：US08754455B2

    公开(公告)日：2014-06-17

    申请号：US12983489

    申请日：2011-01-03

    申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

    发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

    IPC分类号： H01L29/80

    CPC分类号： H01L29/66916 ,  H01L27/14679 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/808 ,  H01L29/8086

    摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

    摘要翻译： 公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。 具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性 ）。 通过明确定义该结，N型沟道区中的耗尽层延伸。 延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。 本文还公开了形成这种JFET结构的方法的实施例。

    Schottky barrier diode, a method of forming the diode and a design structure for the diode
    4.
    发明授权
    Schottky barrier diode, a method of forming the diode and a design structure for the diode 有权
    肖特基势垒二极管，形成二极管的方法和二极管的设计结构

    公开(公告)号：US08519478B2

    公开(公告)日：2013-08-27

    申请号：US13019716

    申请日：2011-02-02

    申请人： Robert M. Rassel ,  Mark E. Stidham

    发明人： Robert M. Rassel ,  Mark E. Stidham

    IPC分类号： H01L29/06

    CPC分类号： H01L29/66143 ,  G06F17/5068 ,  H01L29/872

    摘要： Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.

    摘要翻译： 公开了肖特基势垒二极管的实施例。 该二极管可以形成在具有第一导电类型的掺杂区域的半导体衬底中。 沟槽隔离结构可以横向围绕衬底顶表面处的掺杂区域的一部分。 半导体层可以位于衬底的顶表面上。 该半导体层可以在掺杂区域的限定部分上方具有肖特基势垒部分，并且在沟槽隔离结构之上的护套部分横向围绕肖特基势垒部分。 肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。 金属硅化物层可以覆盖半导体层。 还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

    Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure
    5.
    发明授权
    Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure 有权
    半导体器件包括非对称轻掺杂漏极（LDD）区域，相关方法和设计结构

    公开(公告)号：US08518782B2

    公开(公告)日：2013-08-27

    申请号：US12963054

    申请日：2010-12-08

    申请人： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark E. Stidham

    发明人： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark E. Stidham

    IPC分类号： H01L21/426

    CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

    摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。 还公开了相关的方法和设计结构。

    Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET
    6.
    发明授权
    Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET 有权
    非对称绝缘体上硅（SOI）结场效应晶体管（JFET）和形成非对称SOI JFET的方法

    公开(公告)号：US08466501B2

    公开(公告)日：2013-06-18

    申请号：US12784583

    申请日：2010-05-21

    申请人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

    发明人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

    IPC分类号： H01L29/808

    CPC分类号： G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/8086

    摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).

    摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。

    LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE
    10.
    发明申请
    LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE 有权
    SOI衬底中的横向高压连接变压器二极管

    公开(公告)号：US20120199907A1

    公开(公告)日：2012-08-09

    申请号：US13449419

    申请日：2012-04-18

    申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L27/12 ,  G06F17/50

    CPC分类号： H01L29/93 ,  H01L29/7391

    摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

    摘要翻译： 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。