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84 条记录 (耗时 0.026 秒)

    Disabling unused/inactive resources in an integrated circuit for static power reduction
    2.
    发明授权
    Disabling unused/inactive resources in an integrated circuit for static power reduction 有权
    禁用集成电路中的未使用/不活动资源以实现静态功耗降低

    公开(公告)号：US08099691B1

    公开(公告)日：2012-01-17

    申请号：US12491174

    申请日：2009-06-24

    申请人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： G06F17/50

    CPC分类号： H03K19/17784

    摘要： A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

    摘要翻译： 公开了一种操作集成电路（“IC”）的方法。 该方法包括识别不在电路设计中使用的IC中的一个或多个未使用或非活动资源，或者在IC运行期间不活动的资源。 该方法还包括启用将用于电路设计中的IC的资源，以及响应于存储在存储单元中的配置值，从一个或多个电源端子禁用IC的一个或多个未使用或不活动的资源。

    Integral metal structure with conductive post portions
    4.
    发明申请
    Integral metal structure with conductive post portions 有权
    具有导电柱部分的整体金属结构

    公开(公告)号：US20100187665A1

    公开(公告)日：2010-07-29

    申请号：US12321833

    申请日：2009-01-26

    申请人： Robert O. Conn

    发明人： Robert O. Conn

    IPC分类号： H01L23/48 ,  H01L21/302 ,  H01L21/31

    CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.

    摘要翻译： 多个FPGA管芯设置在半导体衬底上。 为了提供多个FPGA芯片所需的巨大功率，功率从位于半导体衬底另一侧的厚金属层和大的整体金属结构垂直地穿过半导体衬底。 由于半导体衬底与与衬底接触的金属层具有不同的热线性膨胀系数，所以当结构经受温度变化时，可能发生分层。 为了防止与半导体衬底连接并与整体金属结构电接触的金属层的分层，整体金属结构被制成具有一定数量的柱部分。 在温度变化期间，整体金属结构的后部相对于连接到半导体衬底的金属层弯曲和滑动，并且防止否则会引起分层的线性应力。

    Through-substrate power-conducting via with embedded capacitance
    7.
    发明申请
    Through-substrate power-conducting via with embedded capacitance 审中-公开
    具有嵌入式电容的通过衬底的导电通孔

    公开(公告)号：US20090267183A1

    公开(公告)日：2009-10-29

    申请号：US12150529

    申请日：2008-04-28

    申请人： Dorota Temple ,  Robert O. Conn

    发明人： Dorota Temple ,  Robert O. Conn

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05599

    摘要： When integrated circuits are mounted on a substrate, little space is often available for the required large number of bypass capacitors. A novel substrate structure therefore includes many closely spaced through-holes that extend from a first surface of the substrate to a second surface of the substrate. Each through-hole includes a first conducting layer, a dielectric layer, and a second conducting layer. The first and second conducting layers and the intervening dielectric layer constitute a via having a substantial capacitance (one picofarad). Some of the many vias provide bypass capacitance directly under the integrated circuits. A first set of vias supplies power from a power bus bar on one side of the substrate to the integrated circuits on the other side. A second set of vias sinks current from the integrated circuits on the other side, through the substrate, and to a ground bus bar on the one side.

    摘要翻译： 当集成电路安装在基板上时，通常对所需的大量旁路电容器几乎没有空间。 因此，新颖的衬底结构包括从衬底的第一表面延伸到衬底的第二表面的许多紧密间隔的通孔。 每个通孔包括第一导电层，电介质层和第二导电层。 第一和第二导电层和介入介电层构成具有相当大电容（一个皮法）的通孔。 许多通孔中的一些直接在集成电路下提供旁路电容。 第一组通孔从基板一侧的电源母线供给另一侧的集成电路。 第二组通孔从另一侧的集成电路，通过基板和一侧的接地母线吸收电流。

    Tuning programmable logic devices for low-power design implementation
    8.
    发明授权
    Tuning programmable logic devices for low-power design implementation 有权
    调整可编程逻辑器件，实现低功耗设计

    公开(公告)号：US07549139B1

    公开(公告)日：2009-06-16

    申请号：US10783216

    申请日：2004-02-20

    申请人： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    发明人： Tim Tuan ,  Jan L. deJong ,  Kameswara K. Rao ,  Robert O. Conn

    IPC分类号： G06F17/50 ,  H03K19/00

    CPC分类号： H03K19/17784 ,  G11C5/14 ,  H03K3/356173 ,  H03K19/0016 ,  H03K19/17792

    摘要： A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

    摘要翻译： 一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组 可编程逻辑器件的有源块。 执行时序分析以确定每个活动块中的最大可用时序松弛。 具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。 具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。 结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。