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    Multiplexed video digitization system and method
    1.
    发明授权
    Multiplexed video digitization system and method 有权
    多路复用视频数字化系统及方法

    公开(公告)号：US07480012B1

    公开(公告)日：2009-01-20

    申请号：US11066711

    申请日：2005-02-24

    申请人： Robert Y. Greenberg

    发明人： Robert Y. Greenberg

    IPC分类号： H04N5/268

    CPC分类号： H04N9/64 ,  H04N5/4401 ,  H04N9/641 ,  H04N21/42607

    摘要： The invention relates to a multiplexed video digitization system and method. The system includes a plurality of analog video signals, a multiplexer to select one of the plurality of analog video signals, and an analog-to-digital converter to convert the selected analog video signal into a digital video signal. The plurality of analog video signals may include component video signals, red, green, and blue signals, or s-video signals. The multiplexer may include control logic to select the one of the plurality of analog video signals. The system may include a plurality of sample and hold circuits to insure time aligned sampling of the corresponding plurality of video signals.

    摘要翻译： 本发明涉及多路视频数字化系统和方法。 该系统包括多个模拟视频信号，多路复用器，用于选择多个模拟视频信号中的一个;以及模数转换器，用于将所选择的模拟视频信号转换为数字视频信号。 多个模拟视频信号可以包括分量视频信号，红色，绿色和蓝色信号，或S视频信号。 复用器可以包括用于选择多个模拟视频信号之一的控制逻辑。 该系统可以包括多个采样和保持电路，以确保对应的多个视频信号的时间对准采样。

    Ultra-high bandwidth multi-port memory system for image scaling applications
    2.
    发明授权
    Ultra-high bandwidth multi-port memory system for image scaling applications 有权
    用于图像缩放应用的超高带宽多端口存储器系统

    公开(公告)号：US06903733B1

    公开(公告)日：2005-06-07

    申请号：US10405775

    申请日：2003-04-01

    申请人： Robert Y. Greenberg ,  Michael G. West

    发明人： Robert Y. Greenberg ,  Michael G. West

    IPC分类号： G06T3/40 ,  G09G5/391 ,  G09G5/395 ,  G09G5/00

    CPC分类号： G06T3/4084 ,  G09G5/391 ,  G09G5/395 ,  G09G2340/0407

    摘要： The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers. The plurality of output buffers provides the vertical scalar with simultaneous parallel access to multiple lines of buffered digital image data. The frame memory preferably comprises DRAM that stores the image data such that row faults are minimized. The DRAM frame memory preferably includes at least two memory banks, each including a plurality of rows and a plurality of columns. The DRAM frame memory has multiple purposes including storing digital image data frames for sample rate conversion, as well as, storing bitmaps for access by an On Screen Display controller and storing microprocessor data for access by a microprocessor.

    摘要翻译： 本发明的图像缩放存储器系统通过使用与输入缓冲器耦合的现有帧存储器和用于提供具有同时并行访问多条数据线的多个输出缓冲器来消除内部或外部线路存储器的使用。 此外，包括帧存储器的本发明的图像缩放存储器系统被嵌入到集成电路中。 因此，本发明的图像缩放电路提高了可靠性，降低了成本，并提高了硅面积的使用。 帧存储器耦合到输入侧的输入缓冲器和输出侧的多个输出缓冲器。 多个输出缓冲器位于帧存储器和垂直标量之间。 每个输出缓冲器顺序地从帧缓冲器访问并传送图像行的部分。 每个输出缓冲器仅存储图像行的一部分，导致相对较小的输出缓冲器。 多个输出缓冲器提供具有同时并行访问多行缓冲数字图像数据的垂直标量。 帧存储器优选地包括存储图像数据的DRAM，使得行故障被最小化。 DRAM帧存储器优选地包括至少两个存储体，每个存储体包括多个行和多个列。 DRAM帧存储器具有多种用途，包括存储用于采样率转换的数字图像数据帧，以及存储用于由屏幕显示控制器访问的位图，并存储微处理器数据以供微处理器访问。

    Ultra-high bandwidth multi-port memory system for image scaling applications
    3.
    发明授权
    Ultra-high bandwidth multi-port memory system for image scaling applications 有权
    用于图像缩放应用的超高带宽多端口存储器系统

    公开(公告)号：US06611260B1

    公开(公告)日：2003-08-26

    申请号：US09313060

    申请日：1999-05-17

    申请人： Robert Y. Greenberg ,  Michael G. West

    发明人： Robert Y. Greenberg ,  Michael G. West

    IPC分类号： G09G500

    CPC分类号： G06T3/4023 ,  G09G5/391 ,  G09G5/395 ,  G09G2340/0407

    摘要： The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers. The plurality of output buffers provides the vertical scalar with simultaneous parallel access to multiple lines of buffered digital image data. The frame memory preferably comprises DRAM that stores the image data such that row faults are minimized. The DRAM frame memory preferably includes at least two memory banks, each including a plurality of rows and a plurality of columns. The DRAM frame memory has multiple purposes including storing digital image data frames for sample rate conversion, as well as, storing bitmaps for access by an On Screen Display controller and storing microprocessor data for access by a microprocessor.

    摘要翻译： 本发明的图像缩放存储器系统通过使用与输入缓冲器耦合的现有帧存储器和用于提供具有同时并行访问多条数据线的多个输出缓冲器来消除内部或外部线路存储器的使用。 此外，包括帧存储器的本发明的图像缩放存储器系统被嵌入到集成电路中。 因此，本发明的图像缩放电路提高了可靠性，降低了成本，并提高了硅面积的使用。 帧存储器耦合到输入侧的输入缓冲器和输出侧的多个输出缓冲器。 多个输出缓冲器位于帧存储器和垂直标量之间。 每个输出缓冲器顺序地从帧缓冲器访问并传送图像行的部分。 每个输出缓冲器仅存储图像行的一部分，导致相对较小的输出缓冲器。 多个输出缓冲器提供具有同时并行访问多行缓冲数字图像数据的垂直标量。 帧存储器优选地包括存储图像数据的DRAM，使得行故障被最小化。 DRAM帧存储器优选地包括至少两个存储体，每个存储体包括多个行和多个列。 DRAM帧存储器具有多种用途，包括存储用于采样率转换的数字图像数据帧，以及存储用于由屏幕显示控制器访问的位图，并存储微处理器数据以供微处理器访问。