公开(公告)号：US20110037630A1

公开(公告)日：2011-02-17

申请号：US12603883

申请日：2009-10-22

Applicant: Roderick McLACHLAN ,  Samuel BLACKBURN

Inventor： Roderick McLACHLAN ,  Samuel BLACKBURN

IPC: H03M1/10

CPC classification number: H03M1/1019 ,  H03M1/785

Abstract: The invention is a novel scheme of calibrating a voltage-mode digital to analog converter using a current-mode digital to analog converter. A DAC system is comprised of a voltage-mode DAC with an R-2R architecture structure and includes a ROM lookup table where calibration codes associated with each of a plurality of input codes are stored. A reference current is scaled with the calibration codes to output a calibration current that induces adjustments in an output voltage to counteract non-linearities that may be induced by resistor mismatch.

Abstract translation: 本发明是使用电流模式数模转换器校准电压模式数模转换器的新颖方案。 DAC系统由具有R-2R架构结构的电压模式DAC组成，并且包括ROM查找表，其中存储与多个输入代码中的每一个相关联的校准代码。 参考电流用校准代码缩放以输出校准电流，其引起输出电压的调整以抵消可能由电阻器失配引起的非线性。

公开(公告)号：US20100315277A1

公开(公告)日：2010-12-16

申请号：US12483295

申请日：2009-06-12

Applicant: Roderick MCLACHLAN

Inventor： Roderick MCLACHLAN

IPC: H03M1/80 ,  H03M1/66

CPC classification number: H03M1/0845 ,  H03M1/76 ,  H03M1/785 ,  H03M1/808

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell. When an op amp drives particular cells, sense switches generate multiple a feedback paths to the driving op amp, which permits the op amp to drive the selected cell resistors at voltages that overcomes any voltage losses induces by associated force switches, and cancels the effect of any variation in the voltage losses induced by different force switches. The switch-controlled cells find application in a variety of DAC architectures, including binary weighted R2R architectures, equally-weighted segmented architectures or hybrid architectures that blend principles of R2R and segmented architectures.

Abstract translation: 数模转换器（DAC）包括一对运算放大器，每个运算放大器具有耦合到相应的高或低参考电压的第一输入。 DAC包括多个开关控制单元，每个单元包括电阻器和两个力/感测开关对。 在每个单元内，所有四个开关都耦合到电阻器。 第一力开关耦合到第一运算放大器的输出，相关联的感测开关耦合到第一运算放大器的反相输入端。 第二力开关耦合到第二运算放大器的输出，相关联的感测开关耦合到第二运算放大器的反相输入端。 因此，力开关提供选择性的导电路径以允许运算放大器驱动给定的电池。 当运算放大器驱动特定单元时，感测开关产生到驱动运算放大器的多个反馈路径，这允许运算放大器以克服由相关力开关引起的任何电压损耗的电压驱动所选择的单元电阻，并且消除任何 由不同的力开关引起的电压损耗的变化。 交换机控制的小区在各种DAC体系结构中找到应用，包括二进制加权的R2R架构，同等加权的分段架构或混合R2R和分段架构的混合体系结构。

公开(公告)号：US20070090875A1

公开(公告)日：2007-04-26

申请号：US11256714

申请日：2005-10-24

Applicant: Roderick McLachlan ,  Alan Gillespie ,  Teng-Hee Lee

Inventor： Roderick McLachlan ,  Alan Gillespie ,  Teng-Hee Lee

IPC: H03F1/36

CPC classification number: H03F3/45475 ,  H03F1/34 ,  H03F2203/45522 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

Abstract: A feedback circuit for an operational amplifier is provided, the circuit comprising a first impedance element in a current flow path between an output of the operational amplifier and a first node, wherein a plurality of impedance elements are, in response to a control signal, selectively connectable either between the first node and a first input of the operational amplifier, or between the first node and a further node, and the further node and the first input of the operational amplifier are at the same potential such that a voltage at the first node is independent of the control signal.

Abstract translation: 提供了一种用于运算放大器的反馈电路，该电路包括在运算放大器的输出与第一节点之间的电流流动路径中的第一阻抗元件，其中多个阻抗元件响应于控制信号而选择性地 可以在第一节点和运算放大器的第一输入端之间或者在第一节点和另一节点之间连接，并且运算放大器的另一节点和第一输入端处于相同的电位，使得第一节点处的电压 独立于控制信号。

公开(公告)号：US09136866B2

公开(公告)日：2015-09-15

申请号：US14050081

申请日：2013-10-09

Applicant: Fergus John Downey ,  Roderick McLachlan

Inventor： Fergus John Downey ,  Roderick McLachlan

IPC: H03M1/66 ,  H03M1/78 ,  H03M1/12 ,  H03M1/74 ,  H03M1/00

CPC classification number: H03M1/785 ,  H03M1/00 ,  H03M1/069 ,  H03M1/12 ,  H03M1/664 ,  H03M1/687 ,  H03M1/747

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract translation: 一种数模转换器（DAC），包括具有在DAC中形成二进制加权值的第一多个电流流路的第一部分; 以及第二部分，其连接到所述第一部分并且具有第二多个电流流动路径，其中所述第一和第二多个电流流动路径中的每一个可在第一和第二节点之间切换，并且其中所述第二多个电流流中的一个或多个的权重 电流流动路径意图等于第一多个当前流动路径中的一个或多个的权重，以便在第一部分中提供冗余。

公开(公告)号：US20150097712A1

公开(公告)日：2015-04-09

申请号：US14050081

申请日：2013-10-09

Applicant: Fergus John DOWNEY ,  Roderick McLACHLAN

Inventor： Fergus John DOWNEY ,  Roderick McLACHLAN

IPC: H03M1/78 ,  H03M1/66

CPC classification number: H03M1/785 ,  H03M1/00 ,  H03M1/069 ,  H03M1/12 ,  H03M1/664 ,  H03M1/687 ,  H03M1/747

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract translation: 一种数模转换器（DAC），包括具有在DAC中形成二进制加权值的第一多个电流流路的第一部分; 以及第二部分，其连接到所述第一部分并且具有第二多个电流流动路径，其中所述第一和第二多个电流流动路径中的每一个可在第一和第二节点之间切换，并且其中所述第二多个电流流中的一个或多个的权重 电流流动路径意图等于第一多个当前流动路径中的一个或多个的权重，以便在第一部分中提供冗余。

公开(公告)号：US08988259B2

公开(公告)日：2015-03-24

申请号：US13770064

申请日：2013-02-19

Applicant: Avinash Gutta ,  Alan Gillespie ,  Roderick McLachlan

Inventor： Avinash Gutta ,  Alan Gillespie ,  Roderick McLachlan

IPC: H03M1/00 ,  H03K3/356 ,  H03M1/66 ,  H03K17/00

CPC classification number: H03K3/356139 ,  H03K17/00 ,  H03K17/16 ,  H03M1/66

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract translation: 数据转换器可以包括电阻器网络，连接到电阻器网络的开关网络，并且具有多个开关电路，每个开关电路各自具有NMOS和PMOS开关晶体管，以及电压发生器，用于产生用于驱动栅极的驱动电压 至少一个开关电路的NMOS或PMOS开关晶体管中的至少一个。 电压发生器可以包括第一和第二对晶体管，每对晶体管具有连接的控制端子，并且连接到第二NMOS或PMOS晶体管，第一或第二电阻器以及另一对晶体管。 第一和第二电阻器可具有基本相等的电阻值。 第二NMOS与PMOS晶体管的宽比比可以与开关电路NMOS与PMOS晶体管的这一比例基本相等。

公开(公告)号：US08537043B1

公开(公告)日：2013-09-17

申请号：US13445183

申请日：2012-04-12

Applicant: Roderick McLachlan ,  Avinash Gutta ,  Fergus Downey

Inventor： Roderick McLachlan ,  Avinash Gutta ,  Fergus Downey

IPC: H03M1/66

CPC classification number: H03K17/063 ,  H03M1/785

Abstract: A digital-to-analog converter (DAC) includes a resistor leg that is switchably connected to a first voltage reference via an n-channel MOSFET and to a second voltage reference via a p-channel MOSFET, and a generator circuit. The generator circuit further includes a first sub-circuit for generating a drive voltage (Vgn) and a second sub-circuit for a) offsetting the first drive voltage by an offset voltage to generate a second drive voltage, and b) supplying the second drive voltage to a gate of one of the first NMOS and the first PMOS.

Abstract translation: 数模转换器（DAC）包括电阻支路，其经由n沟道MOSFET可切换地连接到第一参考电压，并通过p沟道MOSFET和发电机电路连接到第二参考电压。 发电机电路还包括用于产生驱动电压（Vgn）的第一子电路和用于a）使第一驱动电压偏移偏移电压以产生第二驱动电压的第二子电路，以及b）提供第二驱动 电压到第一NMOS和第一PMOS之一的栅极。

公开(公告)号：US20070096965A1

公开(公告)日：2007-05-03

申请号：US11266041

申请日：2005-11-03

Applicant: Alan Gillespie ,  Roderick McLachlan ,  Teng-Hee Lee

Inventor： Alan Gillespie ,  Roderick McLachlan ,  Teng-Hee Lee

IPC: H03M1/66

CPC classification number: H03M1/0607 ,  H03M1/785

Abstract: A digital to analog converter comprising: a digital to analog conversion core adapted to receive at least one reference voltage and a digital word to be converted, and to output an analog voltage as a function of the digital word and the at least one reference voltage; a sensing circuit for sensing a difference between a first ground voltage associated with an output of the digital to analog converter and a ground reference voltage occurring at the digital to analog converter; and a compensation circuit for applying a compensation voltage to the at least one reference voltage used by the conversion core of the digital to analog converter.

公开(公告)号：US08089380B2

公开(公告)日：2012-01-03

申请号：US12603883

申请日：2009-10-22

Applicant: Roderick McLachlan ,  Samuel Blackburn

Inventor： Roderick McLachlan ,  Samuel Blackburn

IPC: H03M1/10

CPC classification number: H03M1/1019 ,  H03M1/785

Abstract: The invention is a novel scheme of calibrating a voltage-mode digital to analog converter using a current-mode digital to analog converter. A DAC system is comprised of a voltage-mode DAC with an R-2R architecture structure and includes a ROM lookup table where calibration codes associated with each of a plurality of input codes are stored. A reference current is scaled with the calibration codes to output a calibration current that induces adjustments in an output voltage to counteract non-linearities that may be induced by resistor mismatch.

Abstract translation: 本发明是使用电流模式数模转换器校准电压模式数模转换器的新颖方案。 DAC系统由具有R-2R架构结构的电压模式DAC组成，并且包括ROM查找表，其中存储与多个输入代码中的每一个相关联的校准代码。 参考电流用校准代码缩放以输出校准电流，其引起输出电压的调整以抵消可能由电阻器失配引起的非线性。

公开(公告)号：US08514112B2

公开(公告)日：2013-08-20

申请号：US13168017

申请日：2011-06-24

Applicant: Roderick McLachlan ,  Michael Coln

Inventor： Roderick McLachlan ,  Michael Coln

IPC: H03M1/06

CPC classification number: H03M1/0621 ,  H03M1/1047 ,  H03M1/804 ,  H03M1/808

Abstract: The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.

Abstract translation: 本发明提供耦合到转换器的系统误差校正网络。 转换器可能会显示系统的非线性误差，并且系统误差校正网络对于非线性误差，形成像反失真函数一样的校正变换函数。 然后，系统误差校正网络根据参考变量对校正变换函数进行缩放，其中非线性误差的大小与参考变量相关。 然后将缩放的校正变换函数应用于转换器路径，以便产生校正的模拟输出信号。