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    Early energy measurement
    2.
    发明授权
    Early energy measurement 有权
    早期能量测量

    公开(公告)号：US07991085B2

    公开(公告)日：2011-08-02

    申请号：US11427651

    申请日：2006-06-29

    申请人： Ron Shalev

    发明人： Ron Shalev

    IPC分类号： H04L27/28

    CPC分类号： H03G3/3078 ,  H04L27/2607 ,  H04L27/2647

    摘要： In a described implementation of early energy measurement, a wireless device adjusts a receiver gain during each current symbol time responsive to a signal energy level measured in a previous symbol time.

    摘要翻译： 在所描述的早期能量测量的实现中，无线设备响应于在先前符号时间中测量的信号能级而调整在每个当前符号时间期间的接收机增益。

    Method and apparatus for cutting senior store latency using store prefetching
    4.
    发明授权
    Method and apparatus for cutting senior store latency using store prefetching 有权
    使用存储预取来切割高级存储延迟的方法和装置

    公开(公告)号：US09405545B2

    公开(公告)日：2016-08-02

    申请号：US13993508

    申请日：2011-12-30

    申请人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

    发明人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

    IPC分类号： G06F12/08 ,  G06F9/38

    CPC分类号： G06F9/3814 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0808 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/62

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

    摘要翻译： 根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。 这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

    ENERGY AND AREA OPTIMIZED HETEROGENEOUS MULTIPROCESSOR FOR CASCADE CLASSIFIERS
    7.
    发明申请
    ENERGY AND AREA OPTIMIZED HETEROGENEOUS MULTIPROCESSOR FOR CASCADE CLASSIFIERS 审中-公开
    能源和区域优化分类器的异构多重分配器

    公开(公告)号：US20160275043A1

    公开(公告)日：2016-09-22

    申请号：US14662089

    申请日：2015-03-18

    申请人： Edward T. Grochowski ,  Michael E. Kounavis ,  Ron Shalev

    发明人： Edward T. Grochowski ,  Michael E. Kounavis ,  Ron Shalev

    IPC分类号： G06F15/80 ,  G06F9/38

    CPC分类号： G06F9/3887 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3869 ,  G06F9/3885

    摘要： In one embodiment, a heterogeneous multicore processor is described that is optimized to execute multi-stage computer vision algorithms such as cascade classifier workloads. In such embodiment the heterogeneous processor includes at least one SIMD core, such as a vector processor core, coupled with one or more scalar cores. In one embodiment the heterogeneous multiprocessor executes multi-stage compute operations, where the SIMD core computes a first set of stages and the one or more scalar cores compute the second set of stages. In one embodiment, a process for designing a heterogeneous multicore processor is disclosed which optimizes the ratio of scalar to SIMD cores based on execution time of the multi-stage compute operation in relation to processor die area consumed by a processor configuration having the ratio.

    摘要翻译： 在一个实施例中，描述了被优化以执行诸如级联分类器工作负载的多级计算机视觉算法的异构多核处理器。 在这种实施例中，异构处理器包括与一个或多个标量核耦合的至少一个SIMD核，例如向量处理器核。 在一个实施例中，异构多处理器执行多阶段计算操作，其中SIMD核心计算第一组阶段，并且一个或多个标量核心计算第二组阶段。 在一个实施例中，公开了一种用于设计异构多核处理器的过程，其基于多级计算操作的执行时间相对于具有该比率的处理器配置消耗的处理器管芯面积来优化标量到SIMD核的比率。

    METHOD AND APPARATUS FOR CUTTING SENIOR STORE LATENCY USING STORE PREFETCHING
    8.
    发明申请
    METHOD AND APPARATUS FOR CUTTING SENIOR STORE LATENCY USING STORE PREFETCHING 有权
    使用商店预购切割高级商店的方法和装置

    公开(公告)号：US20140223105A1

    公开(公告)日：2014-08-07

    申请号：US13993508

    申请日：2011-12-30

    申请人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

    发明人： Stanislav Shwartsman ,  Melih Ozgul ,  Sebastien Hily ,  Shlomo Raikin ,  Raanan Sade ,  Ron Shalev

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3814 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0808 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/62

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

    摘要翻译： 根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。 这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

    APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTIONS
    9.
    发明申请
    APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTIONS 审中-公开
    用于记忆级别生产者消费者指令的装置和方法

    公开(公告)号：US20140208031A1

    公开(公告)日：2014-07-24

    申请号：US13994724

    申请日：2011-12-21

    申请人： Shlomo Raikin ,  Robert Valentine ,  Raanan Sade ,  Julius Yuli Mandelbalt ,  Ron Shalev ,  Larisa Novakovsky

    发明人： Shlomo Raikin ,  Robert Valentine ,  Raanan Sade ,  Julius Yuli Mandelbalt ,  Ron Shalev ,  Larisa Novakovsky

    IPC分类号： G06F12/08 ,  G06T1/60

    CPC分类号： G06F12/0811 ,  G06F9/3828 ,  G06F9/3891 ,  G06F12/0891 ,  G06T1/60

    摘要： An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (CPU). For example, one embodiment of a method comprises: A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising: writing data to a buffer within the producer core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

    摘要翻译： 描述了一种用于在中央处理单元（CPU）内有效地将数据从生产者核心传送到消费者核心的装置和方法。 例如，一种方法的一个实施例包括：一种用于将数据块从中央处理单元（CPU）的生产者核心转移到CPU的消费者核心的方法，包括：将数据写入到所述CPU的生产者核心内的缓冲器 CPU直到指定数据量被写入; 在检测到指定量的数据被写入时，响应地产生驱逐周期，使得将数据从填充缓冲器传送到可由生产者核心和消费者核心访问的高速缓存的逐出循环; 并且在消费者核心检测到数据在高速缓存中可用时，在从消费者核心接收到读取信号时从高速缓存提供数据给消费者核心。

    Early Energy Measurement
    10.
    发明申请
    Early Energy Measurement 有权
    早期能量测量

    公开(公告)号：US20080002792A1

    公开(公告)日：2008-01-03

    申请号：US11427651

    申请日：2006-06-29

    申请人： Ron Shalev

    发明人： Ron Shalev

    IPC分类号： H04L27/08 ,  H04K1/10

    CPC分类号： H03G3/3078 ,  H04L27/2607 ,  H04L27/2647

    摘要： In a described implementation of early energy measurement, a wireless device adjusts a receiver gain during each current symbol time responsive to a signal energy level measured in a previous symbol time.

    摘要翻译： 在所描述的早期能量测量的实现中，无线设备响应于在先前符号时间中测量的信号能级而调整在每个当前符号时间期间的接收机增益。