公开(公告)号：US07345305B2

公开(公告)日：2008-03-18

申请号：US11248719

申请日：2005-10-12

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US07119545B2

公开(公告)日：2006-10-10

申请号：US10711641

申请日：2004-09-29

申请人： Ishtiaq Ahsan ,  Ronald Gene Filippi ,  Roy Charles Iggulden ,  Edward William Kiewra ,  Ping-Chuan Wang

发明人： Ishtiaq Ahsan ,  Ronald Gene Filippi ,  Roy Charles Iggulden ,  Edward William Kiewra ,  Ping-Chuan Wang

IPC分类号： G01R31/08 ,  G01R27/26

CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

摘要翻译： 一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。

公开(公告)号：US06989282B2

公开(公告)日：2006-01-24

申请号：US10815418

申请日：2004-04-01

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US06448173B1

公开(公告)日：2002-09-10

申请号：US09589546

申请日：2000-06-07

申请人： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

发明人： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

摘要翻译： 一种能够可靠地生产铝互连的双镶嵌工艺，其通过常规RIE技术生产的铝互连件具有改善的电迁移特性。 特别地，双镶嵌工艺依赖于PVD-Ti / CVD-TiN阻挡层以产生显示出显着降低的饱和电阻水平和/或抑制电迁移的铝线，特别是在长于100微米的线中。 双镶嵌铝线的电迁移寿命很大程度上取决于材料和材料填充工艺条件。 重要的是，材料和加工的偏差可导致电迁移寿命低于铝RIE互连实现的寿命。 在一个示例中，高达2.5MA / cm 2的电流密度是诱导由于电迁移引起的统计上相关的失败数量所必需的。

公开(公告)号：US09287186B2

公开(公告)日：2016-03-15

申请号：US12128260

申请日：2008-05-28

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/522 ,  H01L23/00 ,  H05K1/09 ,  H05K1/02

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

公开(公告)号：US07388224B2

公开(公告)日：2008-06-17

申请号：US11502196

申请日：2006-08-10

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US07098054B2

公开(公告)日：2006-08-29

申请号：US10783462

申请日：2004-02-20

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

公开(公告)号：US20080224135A1

公开(公告)日：2008-09-18

申请号：US12128260

申请日：2008-05-28

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang ,  Conal Eugene Murray

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang ,  Conal Eugene Murray

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。