公开(公告)号：US20240354477A1

公开(公告)日：2024-10-24

申请号：US18137382

申请日：2023-04-20

申请人： Synopsys, Inc.

发明人： Navneet KAKKAR ,  Sridhar KELADI

IPC分类号： G06F30/327 ,  G06F30/33

CPC分类号： G06F30/327 ,  G06F30/33

摘要： Certain aspects are directed to apparatus and methods for logic synthesis. One example method generally includes: receiving a logic design including a representation of a plurality of registers and ports; detecting one or more constant, equal, or opposite registers or ports of the plurality of registers and ports by analyzing logic across a hierarchy boundary identified for the logic synthesis; and generating a netlist by modifying the logic based on the detection.

公开(公告)号：US12126714B2

公开(公告)日：2024-10-22

申请号：US17328723

申请日：2021-05-24

申请人： Synopsys, Inc.

发明人： Ladvine D. Almeida

IPC分类号： H04L9/08

CPC分类号： H04L9/0861 ,  H04L9/085

摘要： A cryptography system comprises a noising engine and a de-noising engine. The noising engine is configured to receive a key pattern, determine a final membership value based on one or more input parameters and a first knowledge base, and generate a noised key pattern based on the key pattern and the final membership value. The de-noising engine is configured to receive the noised key pattern and the final membership value, and generate a de-noised key pattern based on the noised key pattern, the final membership value, and a second knowledge base.

公开(公告)号：US12124379B2

公开(公告)日：2024-10-22

申请号：US17961473

申请日：2022-10-06

申请人： Synopsys, Inc.

发明人： Karthik Thucanakkenpalayam Sundararajan

IPC分类号： G06F12/0891

CPC分类号： G06F12/0891

摘要： A processing system employs a method to order the elements within a memory. Ordering the elements includes receiving an accessed memory element. The accessed memory element is requested by a processor from a memory. Further, the accessed memory element is compared to stored elements within the memory to generate control signals. Gate control signals from the control signals are generated. The order of the stored elements within the memory is updated based on the gate control signals.

公开(公告)号：US12112202B2

公开(公告)日：2024-10-08

申请号：US16882640

申请日：2020-05-25

申请人： Synopsys, Inc.

发明人： Amit Garg ,  Amit Tara ,  Shripad Deshpande

IPC分类号： G06F9/50 ,  G06F9/455 ,  G06F9/48

CPC分类号： G06F9/5027 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5061 ,  G06F9/5066

摘要： A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device.

公开(公告)号：US12085970B1

公开(公告)日：2024-09-10

申请号：US18106897

申请日：2023-02-07

申请人： Synopsys, Inc.

发明人： Ankit Agrawal ,  Sayan Adhikary ,  Nitin Bansal

IPC分类号： H03K5/08 ,  G05F1/56 ,  H03K17/687

CPC分类号： G05F1/56 ,  H03K5/08 ,  H03K17/6872

摘要： A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate limited voltage signals, each of which is a fraction of voltage between the pad and supply voltage or between the pad and ground. The NMOS clampers and PMOS clampers configured to receive reference voltages and limited voltage signals to generate output, which is in turn input into gate terminals of the subset of NMOS or PMOS transistors.

公开(公告)号：US12082403B1

公开(公告)日：2024-09-03

申请号：US17849413

申请日：2022-06-24

申请人： Synopsys, Inc.

发明人： Andrew Edward Horch ,  Oleg Ivanov ,  Larry Wang

IPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H10B20/20

CPC分类号： H10B20/20 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252

摘要： A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M−1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further includes, in part, M×N anti-fuses. Each anti-fuse is associated and forms a bitcell with a corresponding one of the M×N select transistors.

公开(公告)号：US12079558B2

公开(公告)日：2024-09-03

申请号：US18144685

申请日：2023-05-08

申请人： Synopsys, Inc.

发明人： Deepak D. Sherlekar ,  Basannagouda Reddy ,  Shanie George

IPC分类号： G06F30/392 ,  G06F30/3947 ,  G06F111/20 ,  G06F119/06 ,  G06F119/12

CPC分类号： G06F30/392 ,  G06F30/3947 ,  G06F2111/20 ,  G06F2119/06 ,  G06F2119/12

摘要： On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

公开(公告)号：US20240289524A1

公开(公告)日：2024-08-29

申请号：US18113582

申请日：2023-02-23

申请人： Synopsys, Inc.

发明人： Aaron John BARKER

IPC分类号： G06F30/3308

CPC分类号： G06F30/3308 ,  G06F2119/02

摘要： The present disclosure describes systems and methods for generating a superconducting electronic circuit design. The system includes a memory and a processor. The processor simulates a superconducting electronic circuit design using a first process variation to produce a first score and simulates the superconducting electronic circuit design using a second process variation to produce a second score. The processor, in response to determining that the first score is lower than the second score, simulates the superconducting electronic circuit design using the first process variation and a first design variation to produce a third score and simulates the superconducting electronic circuit design using the first process variation and a second design variation to produce a fourth score. The processor updates the superconducting electronic circuit design using the first process variation and the first design variation in response to determining that the third score is higher than the fourth score.

公开(公告)号：US12057840B1

公开(公告)日：2024-08-06

申请号：US18095436

申请日：2023-01-10

申请人： Synopsys, Inc.

发明人： Yue Yu ,  Kuan Zhou

IPC分类号： H03K3/02 ,  G11C27/02 ,  H03K3/037 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K3/037 ,  G11C27/02 ,  H03K19/1733 ,  H03K19/20

摘要： A single-ended to a differential signal converter (converter) includes, in part, first, second, and third inverting elements, each having a first size, and coupled in series to form a chain of inverting elements. The converter further includes a fourth inverting element of a second size and coupled to the input of the first inverting element, a fifth inverting element of a third size and coupled to an output terminal of the first inverting element, a sixth inverting element of the third size and coupled to an output of the second inverting element, and a seventh inverting element of the second size and coupled to the output of the third inverting element. The outputs of the fourth and sixth inverting elements form a first one of the differential signals. The outputs of the fifth and seventh inverting elements form a second one of the differential signals.

公开(公告)号：US12032894B2

公开(公告)日：2024-07-09

申请号：US17349250

申请日：2021-06-16

申请人： Synopsys, Inc.

发明人： Louis Schaffer ,  Kenter Lin ,  Soo Han Choi

IPC分类号： G06F30/30 ,  G06F30/398 ,  G06F40/55 ,  G06F111/04 ,  G06F113/18 ,  G06F115/02

CPC分类号： G06F30/398 ,  G06F40/55 ,  G06F2111/04 ,  G06F2113/18 ,  G06F2115/02

摘要： A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the exploded cell.