公开(公告)号：US08441021B2

公开(公告)日：2013-05-14

申请号：US13567215

申请日：2012-08-06

申请人： Kunio Hosoya ,  Saishi Fujikawa ,  Takahiro Kasahara

发明人： Kunio Hosoya ,  Saishi Fujikawa ,  Takahiro Kasahara

IPC分类号： H01L29/18 ,  H01L33/00

CPC分类号： H01L21/84 ,  G02F2202/105 ,  H01L27/3262 ,  H01L27/3293 ,  H01L29/66772 ,  H01L51/52

摘要： To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.

摘要翻译： 为了实现显示部分的放大和高清晰度，在像素中使用单晶半导体膜作为晶体管，并且包括以下步骤：将多个单晶半导体衬底接合到基底衬底; 分离所述多个单晶半导体衬底的一部分以在所述基底衬底上形成各自包括单晶半导体膜的多个区域; 形成各自包含所述单晶半导体膜作为沟道形成区域的多个晶体管; 以及在设置有单晶半导体膜的区域和未设置单晶半导体膜的区域上形成多个像素电极。 电连接到形成在未设置单晶半导体膜的区域上的像素电极的一些晶体管形成在设置有单晶半导体膜的区域中。

公开(公告)号：US08344379B2

公开(公告)日：2013-01-01

申请号：US12565854

申请日：2009-09-24

申请人： Saishi Fujikawa ,  Kunio Hosoya

发明人： Saishi Fujikawa ,  Kunio Hosoya

IPC分类号： H01L29/04 ,  H01L33/00

CPC分类号： H01L51/055 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3279 ,  H01L29/4908 ,  H01L51/0023 ,  H01L51/56

摘要： A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming a third conductive film so as to cover the second conductive film formed over the first conductive film, and selectively etching the first conductive film and the third conductive film. Thus, wires using a low resistance material can be formed in a large-sized panel, and thus, a problem of signal delay can be solved.

公开(公告)号：US20090142867A1

公开(公告)日：2009-06-04

申请号：US12325584

申请日：2008-12-01

申请人： Saishi Fujikawa ,  Yoko Chiba

发明人： Saishi Fujikawa ,  Yoko Chiba

IPC分类号： H01L21/336 ,  H01L21/02

CPC分类号： H01L27/1214 ,  H01L27/1288

摘要： The number of photomasks is reduced in a method for manufacturing a liquid crystal display device which operates in a fringe field switching mode, whereby a manufacturing process is simplified and manufacturing cost is reduced. A first transparent conductive film and a first metal film are sequentially stacked over a light-transmitting insulating substrate; the first transparent conductive film and the first metal film are shaped using a multi-tone mask which is a first photomask; an insulating film, a first semiconductor film, a second semiconductor film, and a second metal film are sequentially stacked; the second metal film and the second semiconductor film are shaped using a multi-tone mask which is a second photomask; a protective film is formed; the protective film is shaped using a third photomask; a second transparent conductive film is formed; and the second transparent conductive film is shaped using a fourth photomask.

摘要翻译： 在用于制造在边缘场切换模式下操作的液晶显示装置的方法中，光掩模的数量减少，由此简化了制造工艺并降低了制造成本。 第一透明导电膜和第一金属膜依次层叠在透光绝缘基板上; 使用作为第一光掩模的多色调掩模来成形第一透明导电膜和第一金属膜; 顺序堆叠绝缘膜，第一半导体膜，第二半导体膜和第二金属膜; 使用作为第二光掩模的多色调掩模来成形第二金属膜和第二半导体膜; 形成保护膜; 保护膜使用第三光掩模成形; 形成第二透明导电膜; 并且使用第四光掩模来成形第二透明导电膜。

公开(公告)号：US20090111198A1

公开(公告)日：2009-04-30

申请号：US12254560

申请日：2008-10-20

申请人： Saishi FUJIKAWA ,  Kunio HOSOYA ,  Yoko CHIBA

发明人： Saishi FUJIKAWA ,  Kunio HOSOYA ,  Yoko CHIBA

IPC分类号： H01L21/336 ,  H01L33/00

CPC分类号： H01L27/1288 ,  G02F2001/13606 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2001/13625 ,  G02F2201/50 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214

摘要： A manufacturing method of the present invention includes a process using a first multi-tone mask, in which a first conductive layer in which a transparent conductive layer and a metal layer are stacked over a substrate, a gate electrode formed of a first conductive layer, and a pixel electrode formed of a single layer of the transparent conductive layer are formed, a process using a second multi-tone mask, in which a contact hole to the pixel electrode, and an island of an i-type semiconductor layer and an n+ type semiconductor layer are formed after a gate insulating film, the i-type semiconductor layer, and the n+ type semiconductor layer are formed, a process using a third photomask, in which a source electrode and a drain electrode are formed after a second conductive layer is formed, and a process using a fourth photomask, in which an opening region is formed after a protective film is deposited.

摘要翻译： 本发明的制造方法包括使用第一多色调掩模的工艺，其中在衬底上堆叠透明导电层和金属层的第一导电层，由第一导电层形成的栅电极， 形成由透明导电层的单层形成的像素电极，使用第二多色调掩模的处理，其中与像素电极的接触孔和i型半导体层的岛和n + 在栅极绝缘膜，i型半导体层和n +型半导体层形成之后形成使用第三光掩模的工艺，其中在第二导电层之后形成源电极和漏电极 以及使用第四光掩模的方法，其中在保护膜沉积之后形成开口区域。

公开(公告)号：US20090101906A1

公开(公告)日：2009-04-23

申请号：US12254603

申请日：2008-10-20

申请人： Kunio HOSOYA ,  Saishi Fujikawa

发明人： Kunio HOSOYA ,  Saishi Fujikawa

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78678

摘要： A first resist pattern is formed by exposure using a first multi-tone photomask, and a first conductive layer, a first insulating layer, a first semiconductor layer, and a second semiconductor layer are etched, so that an island-shaped single layer and an island-shaped stack are formed. Here, sidewalls are formed on side surfaces of the island-shaped single layer and the island-shaped stack. Further, a second resist pattern is formed by exposure using a second multi-tone photomask, and a second conductive layer and the second semiconductor layer are etched, so that a thin film transistor, a pixel electrode, and a connection terminal are formed. After that, a third resist pattern is formed by exposure from a rear side using metal layers of the first conductive layer and the second conductive layer as masks, and the third insulating layer are etched, so that a protective insulating layer is formed.

摘要翻译： 通过使用第一多色调光掩模的曝光形成第一抗蚀剂图案，并且蚀刻第一导电层，第一绝缘层，第一半导体层和第二半导体层，使得岛状单层和 形成岛状叠层。 这里，在岛状单层和岛状叠层的侧面形成有侧壁。 此外，通过使用第二多色调光掩模的曝光形成第二抗蚀剂图案，并且蚀刻第二导电层和第二半导体层，从而形成薄膜晶体管，像素电极和连接端子。 之后，使用第一导电层和第二导电层的金属层作为掩模从后侧曝光形成第三抗蚀剂图案，并且蚀刻第三绝缘层，从而形成保护绝缘层。

公开(公告)号：US20080079892A1

公开(公告)日：2008-04-03

申请号：US11902554

申请日：2007-09-24

申请人： Saishi Fujikawa ,  Kunio Hosoya

发明人： Saishi Fujikawa ,  Kunio Hosoya

IPC分类号： G02F1/1339

CPC分类号： G02F1/13394 ,  G02F1/133512 ,  G02F1/1362

摘要： When a columnar spacer is provided in a region overlapping with a TFT, there is a concern that pressure will be applied when attaching a pair of substrates to each other, which may result in the TFT being adversely affected and a crack forming. A dummy layer is formed of an inorganic material below a columnar spacer which is formed in a position overlapping with the TFT. The dummy layer is located in the position overlapping with the TFT, so that pressure applied to the TFT in a step of attaching the pair of substrates is distributed and relieved. The dummy layer is preferably formed of the same material as a pixel electrode so that it is formed without an increase in the number of processing steps.

摘要翻译： 当在与TFT重叠的区域中设置柱状间隔物时，担心当将一对基板彼此连接时施加压力，这可能导致TFT受到不利影响和形成裂纹。 虚设层由形成在与TFT重叠的位置的柱状间隔物下方的无机材料形成。 虚设层位于与TFT重叠的位置，从而在安装一对基板的步骤中施加到TFT的压力被分配和释放。 虚拟层优选由与像素电极相同的材料形成，使得其形成而不增加处理步骤的数量。

公开(公告)号：US20050048744A1

公开(公告)日：2005-03-03

申请号：US10919513

申请日：2004-08-17

申请人： Atsuo Isobe ,  Satoru Saito ,  Saishi Fujikawa

发明人： Atsuo Isobe ,  Satoru Saito ,  Saishi Fujikawa

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  C30B1/00 ,  H01L21/36

CPC分类号： H01L21/02686 ,  H01L21/02672 ,  H01L21/2022 ,  H01L21/2026 ,  H01L29/66757 ,  H01L29/78675 ,  Y10S438/978

摘要： Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been obtained. In the case of operating a CPU with high-speed, the length of a gate (gate length) of a TFT is required to be shorter. However, since a glass substrate has large deflection, a gate electrode cannot have been etched to have a gate length short enough to be used for a CPU. According to the invention, a conductive film is formed over a crystalline semiconductor film formed over a glass substrate, a mask is formed over the conductive film, and the conductive film is etched by using the mask; thus, a thin film transistor with a gate length of 1.0 μm or less is formed. In particular, the crystalline semiconductor film is formed by crystallizing an amorphous semiconductor film formed over a glass substrate by laser irradiation.

摘要翻译： 由于玻璃中含有的钠或玻璃本身具有低耐热性; 没有获得使用在玻璃基板等上形成的TFT制造的CPU。 在高速运行CPU的情况下，TFT的栅极长度（栅极长度）要求较短。 然而，由于玻璃基板具有大的偏转，所以栅极电极不能被蚀刻以具有足够短的栅极长度以用于CPU。 根据本发明，在形成在玻璃基板上的结晶半导体膜上形成导电膜，在导电膜上形成掩模，并使用掩模蚀刻导电膜; 因此，形成栅极长度为1.0μm以下的薄膜晶体管。 特别地，通过激光照射使在玻璃基板上形成的非晶半导体膜结晶化而形成结晶半导体膜。

公开(公告)号：US09006050B2

公开(公告)日：2015-04-14

申请号：US13398883

申请日：2012-02-17

申请人： Kunio Hosoya ,  Saishi Fujikawa

发明人： Kunio Hosoya ,  Saishi Fujikawa

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78678

摘要： A first resist pattern is formed by exposure using a first multi-tone photomask, and a first conductive layer, a first insulating layer, a first semiconductor layer, and a second semiconductor layer are etched, so that an island-shaped single layer and an island-shaped stack are formed. Here, sidewalls are formed on side surfaces of the island-shaped single layer and the island-shaped stack. Further, a second resist pattern is formed by exposure using a second multi-tone photomask, and a second conductive layer and the second semiconductor layer are etched, so that a thin film transistor, a pixel electrode, and a connection terminal are formed. After that, a third resist pattern is formed by exposure from a rear side using metal layers of the first conductive layer and the second conductive layer as masks, and the third insulating layer are etched, so that a protective insulating layer is formed.

摘要翻译： 通过使用第一多色调光掩模的曝光形成第一抗蚀剂图案，并且蚀刻第一导电层，第一绝缘层，第一半导体层和第二半导体层，使得岛状单层和 形成岛状叠层。 这里，在岛状单层和岛状叠层的侧面形成有侧壁。 此外，通过使用第二多色调光掩模的曝光形成第二抗蚀剂图案，并且蚀刻第二导电层和第二半导体层，从而形成薄膜晶体管，像素电极和连接端子。 之后，使用第一导电层和第二导电层的金属层作为掩模从后侧曝光形成第三抗蚀剂图案，并且蚀刻第三绝缘层，从而形成保护绝缘层。

公开(公告)号：US08525183B2

公开(公告)日：2013-09-03

申请号：US13371524

申请日：2012-02-13

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame ,  Takashi Hirosure ,  Saishi Fujikawa

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame ,  Takashi Hirosure ,  Saishi Fujikawa

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/76 ,  H01L31/112 ,  H01L31/062 ,  H01L31/113 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

摘要： A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

公开(公告)号：US08421135B2

公开(公告)日：2013-04-16

申请号：US12323724

申请日：2008-11-26

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Hideaki Kuwabara ,  Saishi Fujikawa

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Hideaki Kuwabara ,  Saishi Fujikawa

IPC分类号： H01L31/062

CPC分类号： H01L27/1222 ,  G02F1/13454 ,  G02F1/13458 ,  H01L27/124 ,  H01L27/156 ,  H01L29/6675 ,  H01L29/66765

摘要： In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.