公开(公告)号：US08291355B2

公开(公告)日：2012-10-16

申请号：US12967851

申请日：2010-12-14

申请人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

发明人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

IPC分类号： G06F17/50

CPC分类号： H03K19/177 ,  H03K19/1737

摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

摘要翻译： 通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分 ）。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

公开(公告)号：US06281704B1

公开(公告)日：2001-08-28

申请号：US09810116

申请日：2001-03-15

申请人： Tony Ngai ,  Sergey Shumarayev ,  Sammy Cheung ,  Rakesh Patel ,  Vinson Chan

发明人： Tony Ngai ,  Sergey Shumarayev ,  Sammy Cheung ,  Rakesh Patel ,  Vinson Chan

IPC分类号： H03K19177

摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

公开(公告)号：US07870513B2

公开(公告)日：2011-01-11

申请号：US11801082

申请日：2007-05-07

申请人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

发明人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/177 ,  H03K19/1737

摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

摘要翻译： 通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分 （“LE”）。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

公开(公告)号：US06489817B1

公开(公告)日：2002-12-03

申请号：US09965290

申请日：2001-09-26

申请人： Choong Kit Wong ,  Sammy Cheung ,  Boon Jin Ang

发明人： Choong Kit Wong ,  Sammy Cheung ,  Boon Jin Ang

IPC分类号： H03K2100

CPC分类号： H03K23/68

摘要： A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.

摘要翻译： 描述了时钟分频器。 时钟分频器包括：正沿触发状态机，具有用于接收第一输入信号的第一输入端和用于提供第一输出信号的第一输出端; 负边缘触发状态机，具有用于接收第二输入信号的第二输入和用于提供第二输出信号的第二输出; 以及耦合到所述正沿触发状态机和所述负沿触发状态机的第一组合逻辑，所述第一组合逻辑具有用于接收第三输入信号的第三输入和用于提供第三输出信号的第三输出，其中（1） 第一输入信号和第二输入信号中的至少一个包括具有输入时钟信号周期的输入时钟信号，（2）第三输入信号包括第一输出信号和第二输出信号，以及（3）第三输出包括 具有输出时钟信号周期的输出时钟信号，其中输出时钟信号周期是输入时钟信号周期的倍数。

公开(公告)号：US6154059A

公开(公告)日：2000-11-28

申请号：US199705

申请日：1998-11-24

申请人： Sammy Cheung ,  John Lam ,  Rakesh Patel ,  Tony Ngai

发明人： Sammy Cheung ,  John Lam ,  Rakesh Patel ,  Tony Ngai

IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/00361

摘要： An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.

摘要翻译： 输出缓冲器具有连接在输入节点和输出节点之间的内部电路。 内部电路包括连接到内部电路的第一组晶体管的静音电压源和连接到内部电路的第二组晶体管的噪声电压源。 嘈杂的电源电压处于高于静态电源的电压电平。 第一组晶体管和第二组晶体管提供噪声电压源和安静电源之间的隔离。 第一组晶体管和第二组晶体管还通过使用至少一个晶体管提供完整的数字高和低内部信号电平，该晶体管可操作地补充第一组晶体管的晶体管的完全截止和导通，第二组晶体管的第二组 一组晶体管。 输出缓冲器还具有接地反弹电路，压摆率控制电路，转换加速器电路，个人计算机接口（PCI）兼容性电路和PCI控制电路。

公开(公告)号：US5572474A

公开(公告)日：1996-11-05

申请号：US503807

申请日：1995-07-18

申请人： Ben Y. Sheen ,  Timothy M. Lacey ,  Sammy Cheung

发明人： Ben Y. Sheen ,  Timothy M. Lacey ,  Sammy Cheung

IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C13/00

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C7/14

摘要： A pseudo-differential sense amplifier for sensing the state of an array memory cell by reference to a reference cell in a predetermined state. The sense amplifier has an input stage coupled to the array memory cell, which provides signals to a differential stage from which an output is generated. The input stage has reference and array side cascode circuits in which the components are matched on each side so as to eliminate process, temperature, and other extraneous variations from influencing the differential output. An enabling signal to the array side of the input stage is delayed with respect to the reference side such that voltage fluctuations externally introduced into the signals passed from the input stage to the differential stage do not cause erroneous switching and/or glitches to appear at the sense amplifier output. Additionally, parallel cascode and load transistors can be selectively switched into the input stage circuit to enable selectable cascode transconductance and circuit loading to effect selectable speed and/or input stage voltage swing.

摘要翻译： 一种伪差分读出放大器，用于通过参考预定状态的参考单元来感测阵列存储单元的状态。 读出放大器具有耦合到阵列存储单元的输入级，其向产生输出的差分级提供信号。 输入级具有参考和阵列侧共源共栅电路，其中组件在每一侧匹配，以消除过程，温度和其他外来变化影响差分输出。 输入级的阵列侧的使能信号相对于参考侧被延迟，使得外部引入到从输入级传递到差分级的信号中的电压波动不会引起错误的切换和/或毛刺出现在 感测放大器输出。 此外，可以将并联共源共栅和负载晶体管选择性地切换到输入级电路，以实现可选择的共源共栅跨导和电路负载来实现可选择的速度和/或输入级电压摆幅。

公开(公告)号：US20070210827A1

公开(公告)日：2007-09-13

申请号：US11801082

申请日：2007-05-07

申请人： Kar Chua ,  Sammy Cheung ,  Hee Phoon ,  Kim Tan ,  Wei Goay

发明人： Kar Chua ,  Sammy Cheung ,  Hee Phoon ,  Kim Tan ,  Wei Goay

IPC分类号： H03K19/173

CPC分类号： H03K19/177 ,  H03K19/1737

摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

摘要翻译： 通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分 （“LE”）。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

公开(公告)号：US06599764B1

公开(公告)日：2003-07-29

申请号：US09870354

申请日：2001-05-30

申请人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

发明人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

IPC分类号： H01L2166

CPC分类号： G01R31/2886 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

摘要翻译： 测试平台被配置为测试具有在第一管芯和第二管芯处的多管芯封装。 测试平台包括一个第一引线，连接到第一个管芯上的VCC输入端。 测试平台还包括连接到第二个芯片上的VCCIO输入的第二引脚。 第二个管芯上的VCC输入端接地。 然后可以使用设置在I / O缓冲器的预驱动器和驱动器之间的控制电路来将第二管芯的I / O引脚三态化。

公开(公告)号：US20130002295A1

公开(公告)日：2013-01-03

申请号：US13614819

申请日：2012-09-13

申请人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

发明人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

IPC分类号： H03K19/173

CPC分类号： H03K19/177 ,  H03K19/1737

摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

摘要翻译： 通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分 ）。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

公开(公告)号：US20110084727A1

公开(公告)日：2011-04-14

申请号：US12967851

申请日：2010-12-14

申请人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

发明人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

IPC分类号： H03K19/177

CPC分类号： H03K19/177 ,  H03K19/1737

摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

摘要翻译： 通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分 （“LE”）。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。