公开(公告)号：US20060220684A1

公开(公告)日：2006-10-05

申请号：US11094974

申请日：2005-03-31

申请人： Samuel Khoo ,  John Kriz ,  Bernard Morris

发明人： Samuel Khoo ,  John Kriz ,  Bernard Morris

IPC分类号： H03K19/094

CPC分类号： H03K19/018507 ,  H03K19/00315

摘要： A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.

摘要翻译： 缓冲电路被配置为产生作为由缓冲电路接收的输入信号的函数的输出信号，缓冲电路响应于控制信号选择性地以至少两种模式之一操作。 在第一模式中，缓冲电路被配置为提供数字缓冲器的特性的低输出阻抗。 在第二模式中，缓冲电路被配置为限制缓冲电路的输出电流。 控制信号表示缓冲电路的输出信号的电平。

公开(公告)号：US20140068122A1

公开(公告)日：2014-03-06

申请号：US13604048

申请日：2012-09-05

申请人： Qiao Shen ,  Samuel Khoo ,  Wen Zhu ,  Lane A. Smith

发明人： Qiao Shen ,  Samuel Khoo ,  Wen Zhu ,  Lane A. Smith

IPC分类号： G06F13/14

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： Methods, systems and processor-readable media for reducing the width of a logical comparison. A width of a logical comparison based on a previous result generated can be recursively reduced from a data stream and a maximum count of consecutive ones or consecutive zeros determined from the serial data stream based on a priority encoder within a single clock cycle in order to avoid a use of complex functions. In this manner, the maximum number of the consecutive ones or the consecutive zeros in a parallel word bus within the single dock cycle can be ascertained.

摘要翻译： 用于减少逻辑比较宽度的方法，系统和处理器可读介质。 基于生成的先前结果的逻辑比较的宽度可以从单个时钟周期内的基于优先级编码器的数据流和从串行数据流确定的连续零的最大计数递归地减少，以避免 使用复杂的功能。 以这种方式，可以确定单个码头周期内的并行字总线中的连续零或连续零的最大数目。

公开(公告)号：US07271614B2

公开(公告)日：2007-09-18

申请号：US11094974

申请日：2005-03-31

申请人： Samuel Khoo ,  John C. Kriz ,  Bernard L. Morris

发明人： Samuel Khoo ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K17/16

CPC分类号： H03K19/018507 ,  H03K19/00315

摘要： A buffer circuit is configured to generate an output signal which is a function of an input signal received by the buffer circuit, the buffer circuit being selectively operative in one of at least two modes in response to a control signal. In a first mode, the buffer circuit is configured to provide a low output impedance, characteristic of a digital buffer. In a second mode, the buffer circuit is configured to limit an output current of the buffer circuit. The control signal is indicative of a level of the output signal of the buffer circuit.

摘要翻译： 缓冲电路被配置为产生作为由缓冲电路接收的输入信号的函数的输出信号，缓冲电路响应于控制信号选择性地以至少两种模式之一操作。 在第一模式中，缓冲电路被配置为提供数字缓冲器的特性的低输出阻抗。 在第二模式中，缓冲电路被配置为限制缓冲电路的输出电流。 控制信号表示缓冲电路的输出信号的电平。

公开(公告)号：US07657799B2

公开(公告)日：2010-02-02

申请号：US11418401

申请日：2006-05-04

申请人： Yasser Ahmed ,  Robert Joseph Kapuschinsky ,  Ashok Khandelwal ,  Samuel Khoo ,  Lane A. Smith

发明人： Yasser Ahmed ,  Robert Joseph Kapuschinsky ,  Ashok Khandelwal ,  Samuel Khoo ,  Lane A. Smith

IPC分类号： G01R31/28

CPC分类号： G06F11/221

摘要： Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

摘要翻译： 公开了用于测试双模式接口的系统和方法。 双模式接口包括第一选通电路和第二选通电路，其被配置为在接口的第一操作模式期间不可操作并且可在接口的第二操作模式期间操作。 双模式接口还包括第一数据电路和第二数据电路，其被配置为在第一操作模式和第二操作模式期间可操作。 双模式接口还包括将第二选通电路的输出与第一选通电路的输入连接的信号线和被配置为响应于接收到测试信号而激活所述信号线的开关元件。

公开(公告)号：US20080010552A1

公开(公告)日：2008-01-10

申请号：US11418401

申请日：2006-05-04

申请人： Yasser Ahmed ,  Robert Kapuschinsky ,  Ashok Khandelwal ,  Samuel Khoo ,  Lane Smith

发明人： Yasser Ahmed ,  Robert Kapuschinsky ,  Ashok Khandelwal ,  Samuel Khoo ,  Lane Smith

IPC分类号： G06F11/00

CPC分类号： G06F11/221

摘要： Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be operable during a first operational mode and inoperable during a second operational mode. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

摘要翻译： 公开了用于测试双模式接口的系统和方法。 双模式接口包括第一选通电路和第二选通电路，其被配置为在第一操作模式期间可操作并且在第二操作模式期间不可操作。 双模式接口还包括第一数据电路和第二数据电路，其被配置为在第一操作模式和第二操作模式期间可操作。 双模式接口还包括将第二选通电路的输出与第一选通电路的输入连接的信号线和被配置为响应于接收到测试信号而激活所述信号线的开关元件。