公开(公告)号：US20080048728A1

公开(公告)日：2008-02-28

申请号：US11845693

申请日：2007-08-27

申请人： Sang-Pyo HONG ,  Jun-Hee LIM

发明人： Sang-Pyo HONG ,  Jun-Hee LIM

IPC分类号： H03F3/45

CPC分类号： H03F3/45179 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C2207/063 ,  H03F1/38 ,  H03F2200/369 ,  H03F2203/45264 ,  H03F2203/45306 ,  H03F2203/45318

摘要： In an embodiment, a sense amplifier can perform a stable differential amplifying operation while having a high differential amplification gain. The sense amplifier comprises a current sense amplification unit, a voltage difference amplification unit, and an output stabilization unit. The current sense amplification unit receives differential input currents and generates differential output voltages corresponding to the differential input currents. The voltage difference amplification unit amplifies a voltage level difference between the differential output voltages through positive feedback using cross-coupled transistors. The output stabilization unit connects output stabilizing elements having a positive input resistance in parallel with the voltage difference amplification unit having a negative input resistance to stabilize the output of the voltage difference amplification unit.

摘要翻译： 在一个实施例中，读出放大器可以执行稳定的差分放大操作，同时具有高的差分放大增益。 读出放大器包括电流检测放大单元，电压差放大单元和输出稳定单元。 电流检测放大单元接收差分输入电流并产生对应于差分输入电流的差分输出电压。 电压差放大单元使用交叉耦合晶体管通过正反馈放大差分输出电压之间的电压电平差。 输出稳定单元将具有正输入电阻的输出稳定元件与具有负输入电阻的电压差放大单元并联，以稳定电压差放大单元的输出。

公开(公告)号：US07227807B2

公开(公告)日：2007-06-05

申请号：US11302606

申请日：2005-12-14

申请人： Sang-Pyo Hong ,  Du-Yeul Kim

发明人： Sang-Pyo Hong ,  Du-Yeul Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

摘要翻译： 配置存储单元阵列块的方法包括将第一单元逻辑块划分为子阵列块并将子阵列块的一部分分配给第二单位逻辑块，其中存储单元阵列块对应于 子阵列块和第二单元逻辑块，并且子阵列块的部分和第二单元逻辑块共享外围电路。 第一单元逻辑块可以基于字线的单位和/或位线的单位被划分为子阵列块。 外围电路可以包括行解码器，列解码器，读出放大器和/或均衡/预充电电路。 还提供了相关寻址方法，存储单元阵列块和半导体存储器件。

公开(公告)号：US20070109904A1

公开(公告)日：2007-05-17

申请号：US11590313

申请日：2006-10-31

申请人： Sang-Pyo Hong ,  Jung-Hwa Lee

发明人： Sang-Pyo Hong ,  Jung-Hwa Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  G11C2207/002 ,  H01L27/10885 ,  H01L27/10897

摘要： A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.

摘要翻译： 存储器芯包括包括多个第一存储器单元的第一子存储器阵列，包括多个第二存储单元的第二子存储器阵列，位线放大电路，被配置为放大第一位线和第二存储器单元之间的电压差 第二位线和包括第一列选择晶体管和第二列选择晶体管的列选择电路，其中第一和第二选择晶体管共享漏极，并将互补位线对电耦合到互补的本地输入/输出线对 ， 分别。 结果，可以减少由于距离不匹配引起的数据错误。

公开(公告)号：US06359459B1

公开(公告)日：2002-03-19

申请号：US09399994

申请日：1999-09-20

申请人： Sei-seung Yoon ,  Sang-pyo Hong

发明人： Sei-seung Yoon ,  Sang-pyo Hong

IPC分类号： G01R3128

CPC分类号： G01R31/40

摘要： Integrated circuits and methods use a margin test voltage generator that is powered at a first power supply voltage to generate a second power supply voltage that has a magnitude that is less than the magnitude of the first power supply voltage. During a low supply voltage margin test, a first logic circuit is powered at the first power supply voltage while a second logic circuit, which is the subject of the test, is powered at the second power supply voltage. As a result, the first power supply voltage may remain at a sufficient magnitude to reliably power other devices or components that are not undergoing the low supply voltage margin test.

摘要翻译： 集成电路和方法使用在第一电源电压下供电的裕度测试电压发生器，以产生具有小于第一电源电压幅度的幅度的第二电源电压。 在低电源电压裕度测试期间，第一逻辑电路以第一电源电压供电，而作为测试对象的第二逻辑电路在第二电源电压下供电。 结果，第一电源电压可能保持在足够的幅度以可靠地对未经历低电源电压裕度测试的其他设备或组件供电。

公开(公告)号：US07605409B2

公开(公告)日：2009-10-20

申请号：US11673403

申请日：2007-02-09

申请人： Soon-Hong Ahn ,  Sang-Pyo Hong

发明人： Soon-Hong Ahn ,  Sang-Pyo Hong

IPC分类号： H01L27/108

CPC分类号： H01L21/823475 ,  H01L27/0207 ,  H01L27/10885

摘要： A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate structure having a pitch. Each second unit circuit has second transistors connected in series, wherein each of the second transistors includes a second gate structure having the pitch. A third transistor and a fourth transistor electrically isolate each of the first and second unit circuits, respectively. An insulation layer covers the first through the fourth transistors. Plugs in the insulation layer are connected to a first gate structure, a second gate structure, a first source region, a first drain region, a second source region or a second drain region. A wiring is connected to the plugs.

摘要翻译： 半导体器件包括第一和第二单元电路。 每个第一单元电路具有串联连接的第一晶体管，其中每个第一晶体管包括具有间距的第一栅极结构。 每个第二单元电路具有串联连接的第二晶体管，其中每个第二晶体管包括具有间距的第二栅极结构。 第三晶体管和第四晶体管分别电隔离第一和第二单元电路中的每一个。 绝缘层覆盖第一至第四晶体管。 绝缘层中的插塞连接到第一栅极结构，第二栅极结构，第一源极区域，第一漏极区域，第二源极区域或第二漏极区域。 接线连接到插头。

公开(公告)号：US20060126419A1

公开(公告)日：2006-06-15

申请号：US11302606

申请日：2005-12-14

申请人： Sang-Pyo Hong ,  Du-Yeul Kim

发明人： Sang-Pyo Hong ,  Du-Yeul Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

摘要翻译： 配置存储单元阵列块的方法包括将第一单元逻辑块划分为子阵列块并将子阵列块的一部分分配给第二单位逻辑块，其中存储单元阵列块对应于 子阵列块和第二单元逻辑块，并且子阵列块的部分和第二单元逻辑块共享外围电路。 第一单元逻辑块可以基于字线的单位和/或位线的单位被划分为子阵列块。 外围电路可以包括行解码器，列解码器，读出放大器和/或均衡/预充电电路。 还提供了相关寻址方法，存储单元阵列块和半导体存储器件。

公开(公告)号：US20050088603A1

公开(公告)日：2005-04-28

申请号：US10989502

申请日：2004-11-17

申请人： Sang-Pyo Hong

发明人： Sang-Pyo Hong

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339

摘要： A seal pattern for a liquid crystal display device includes a substrate having an active area and a non-active area, a main seal pattern having an injection hole arranged in a boundary between the active and non-active areas, and first, second, and third dummy-seal patterns in the non-active area that are arranged along a same direction as a portion of the main seal pattern having the injection hole and spaced apart from each other. The first and second dummy-seal patterns have first and second openings corresponding to opposite ends of the injection hole. The third dummy-seal pattern has third, fourth, and fifth openings arranged alternately in correspondence with the first and second openings.

摘要翻译： 用于液晶显示装置的密封图案包括具有有效面积和非有效面积的基底，主密封图案，其具有布置在活性区域和非活性区域之间的边界中的注入孔，以及第一，第二和/ 非活性区域中的第三虚拟密封图案沿着与具有喷射孔的主密封图案的一部分相同的方向布置并彼此间隔开。 第一和第二虚拟密封图案具有对应于注入孔的相对端的第一和第二开口。 第三虚拟密封图案具有与第一和第二开口相对应地交替设置的第三，第四和第五开口。

公开(公告)号：US06529423B1

公开(公告)日：2003-03-04

申请号：US09511642

申请日：2000-02-22

申请人： Sei-seung Yoon ,  Sang-pyo Hong

发明人： Sei-seung Yoon ,  Sang-pyo Hong

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/22

摘要： An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode. The method includes: inputting an internal clock signal to an internal clock delay circuit, which includes delayers, of a semiconductor device; and inputting CAS latency signals to the internal clock delay circuit to determine CAS latency modes of the semiconductor device; and outputting the internal clock signal through the delay circuits as an output signal of the internal clock signal delay circuit. The internal clock signal passes through one of the delay circuits in a second CAS latency mode and passes through at least two delay circuits among the delay circuits in either a first CAS latency mode or a third CAS latency mode.

摘要翻译： 半导体器件的内部时钟延迟电路和用于延迟半导体器件的内部时钟的方法。 该半导体器件包括CAS等待时间信号发生器，其产生包括第一CAS等待时间信号，第二CAS等待时间信号和第三CAS等待时间信号的CAS等待时间信号，以及接收CAS等待时间信号之一的内部时钟延迟电路， 响应于所接收到的CAS等待时间信号，将内部时钟信号延迟预定时间。 内部时钟延迟电路包括延迟内部时钟信号的延迟电路，并且当半导体器件在第二CAS延迟模式下工作时，内部时钟信号仅通过延迟电路中的一个延迟电路。 该方法包括：将内部时钟信号输入到包括半导体器件的延迟器的内部时钟延迟电路; 并将CAS等待时间信号输入到内部时钟延迟电路，以确定半导体器件的CAS延迟模式; 并通过延迟电路输出内部时钟信号作为内部时钟信号延迟电路的输出信号。 内部时钟信号以第二CAS延迟模式通过其中一个延迟电路，并且在第一CAS延迟模式或第三CAS延迟模式中通过延迟电路中的至少两个延迟电路。

公开(公告)号：US20110128797A1

公开(公告)日：2011-06-02

申请号：US12917602

申请日：2010-11-02

申请人： Sang-Pyo HONG ,  Doo-Young KIM

发明人： Sang-Pyo HONG ,  Doo-Young KIM

IPC分类号： G11C7/06 ,  G11C7/10 ,  H03F3/45

CPC分类号： G11C7/065 ,  G11C7/02 ,  G11C7/1048 ,  G11C2207/005

摘要： A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.

摘要翻译： 公开了一种CMOS锁存型读出放大电路。 所述电路包括CMOS差分放大器，被配置为放大输入线对的电压信号以产生第一放大电压信号对，并将第一放大电压信号对提供给输出线对，第一预充电电压具有第一 电压电平施加到输入线对。 电路还包括CMOS锁存型读出放大器，被配置为放大输出线对的电压信号以产生第二放大电压信号对，并将第二放大电压信号对提供给输出线对。 电路还包括由第一公共使能信号控制并连接到CMOS差分放大器和CMOS锁存器型读出放大器的第一公共节点，使得第一公共使能信号控制CMOS差分放大器和CMOS锁存器 - 型读出放大器。

公开(公告)号：US20100315893A1

公开(公告)日：2010-12-16

申请号：US12815621

申请日：2010-06-15

申请人： Sang Pyo HONG

发明人： Sang Pyo HONG

IPC分类号： G11C7/00 ,  G11C7/06

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4091 ,  G11C11/4094

摘要： A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level.

摘要翻译： 提供了包括CMOS型局部感测放大器电路的半导体存储器件。 半导体存储器件包括第一输入/输出（I / O）线对，预充电到二分之一功率电压电平的第二I / O线对，并从第一I / O线对接收数据，以及 上拉电路将第二I / O对中的一个的电压提升到全电源电压电平。