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    Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein
    3.
    发明授权
    Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein 有权
    具有三维堆叠结构的半导体器件和其中的数据失真的方法

    公开(公告)号：US08488399B2

    公开(公告)日：2013-07-16

    申请号：US13108130

    申请日：2011-05-16

    申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C7/00

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

    Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein
    4.
    发明申请
    Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein 有权
    具有三维堆叠结构的半导体器件及其中的数据偏移方法

    公开(公告)号：US20110286254A1

    公开(公告)日：2011-11-24

    申请号：US13108130

    申请日：2011-05-16

    申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

    Local sense amplifier in memory device
    5.
    发明授权
    Local sense amplifier in memory device 失效
    存储器中的本地读出放大器

    公开(公告)号：US07423896B2

    公开(公告)日：2008-09-09

    申请号：US11789395

    申请日：2007-04-24

    申请人： Sang-Bo Lee

    发明人： Sang-Bo Lee

    IPC分类号： G11C5/06

    CPC分类号： G11C7/18 ,  G11C7/062

    摘要： A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.

    摘要翻译： 存储器件包括一个解码器，它同时设置第一逻辑电平的操作控制信号和列选择线信号。 另外，本地读出放大器具有至少一个开关装置，该开关装置由处于第一逻辑电平的操作控制信号导通，以将至少一个本地I / O线耦合到至少一个全局I / O线。 此外，被设置为并联的信号线从解码器发送操作控制信号和列选择线信号。

    Latency control circuit and method of latency control
    6.
    发明授权
    Latency control circuit and method of latency control 失效
    延迟控制电路和延时控制方法

    公开(公告)号：US07298667B2

    公开(公告)日：2007-11-20

    申请号：US11202314

    申请日：2005-08-12

    申请人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

    发明人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

    IPC分类号： G11C8/00

    CPC分类号： G11C29/023 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

    摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

    摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。

    Methods and circuits for latency control in accessing memory devices
    7.
    发明申请
    Methods and circuits for latency control in accessing memory devices 失效
    访问存储器件时延迟控制的方法和电路

    公开(公告)号：US20050128828A1

    公开(公告)日：2005-06-16

    申请号：US11008462

    申请日：2004-12-09

    申请人： Sang-bo Lee

    发明人： Sang-bo Lee

    IPC分类号： G11C8/00 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407

    CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1072

    摘要： Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in voltage levels provided to the memory. Related circuits are also disclosed.

    摘要翻译： 提供对存储设备的访问的延迟的方法可以包括基于与提供给存储器的电压电平的降低相关联的至少一个参数来调整在存储器操作期间对数据的访问的延迟。 还公开了相关电路。

    Semiconductor memory device with variable plate voltage generator
    8.
    发明授权
    Semiconductor memory device with variable plate voltage generator 失效
    具有可变板电压发生器的半导体存储器件

    公开(公告)号：US5777934A

    公开(公告)日：1998-07-07

    申请号：US674705

    申请日：1996-07-08

    申请人： Sang-bo Lee ,  Dong-il Seo

    发明人： Sang-bo Lee ,  Dong-il Seo

    IPC分类号： G11C11/417 ,  G11C5/14 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4074 ,  G11C8/00

    CPC分类号： G11C11/4074

    摘要： A semiconductor memory device achieves high speed operation while operating at a low power supply voltage by boosting the voltage level at the plate node of a memory cell during an access operation. The memory device includes a plate voltage generator which generates a variable voltage level. The plate voltage generator includes a pair of switches for coupling the plate node to either a conventional (1/2)VCC voltage generator or a power supply node in response to a control signal. The plate voltage generator also includes a pulse generator that generates a pulse signal for controlling the switches in response to the control signal. During a precharge period, the bitline pair is charged to VCC. The plate voltage generator charges the plate node to (1/2)VCC during the precharge state and then to VCC during an access operation. This boosts the voltage level at the storage node of the memory cell, thereby decreasing the time required to amplify the signals on the bitlines.

    摘要翻译： 半导体存储器件在访问操作期间通过升高存储器单元的板节点处的电压电平，在低电源电压下工作，实现高速操作。 存储器件包括产生可变电压电平的板电压发生器。 板电压发生器包括一对开关，用于响应于控制信号将板节点耦合到常规（+ E，fra 1/2 + EE）VCC电压发生器或电源节点。 板电压发生器还包括脉冲发生器，其产生用于响应于控制信号控制开关的脉冲信号。 在预充电期间，位线对被充电到VCC。 板电压发生器在预充电状态期间将板节点充电到（+ E，fra 1/2 + EE）VCC，然后在访问操作期间向VCC充电。 这提高了存储单元的存储节点处的电压电平，从而减少放大位线上的信号所需的时间。

    Sense amplifier for integrated circuit memory devices having boosted sense and current drive capability and methods of operating same
    9.
    发明授权
    Sense amplifier for integrated circuit memory devices having boosted sense and current drive capability and methods of operating same 失效
    具有增强的感测和电流驱动能力的集成电路存储器件的感测放大器及其操作方法

    公开(公告)号：US5701268A

    公开(公告)日：1997-12-23

    申请号：US701892

    申请日：1996-08-23

    申请人： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

    发明人： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

    CPC分类号： G11C7/06 ,  G11C11/4091

    摘要： Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

    摘要翻译： 集成电路存储器件包括电耦合到读出放大器的相应第一和第二感测位信号线的至少第一和第二存储器单元。 感测放大器包括用于通过将这些线驱动到相应的第一和第二不同电位来放大第一和第二感测位信号线之间的电位差的电路。 还提供驱动电路，用于响应于施加升压控制信号，同时将第一和第二感测位信号线驱动朝向第一电位。 该驱动电路优选地包括串联电连接在升压控制输入和第一感测位信号线之间的第一电容器和串联电连接在升压控制输入和第二感测位信号线之间的第二电容器。 升压控制信号被建立在第一电位，以驱动来自不同中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E，fra 1/2 + EE VCC）的感测位信号线朝着第一 在由感测放大器放大第一和第二感测位信号线之间的电位差之前的电位。 本发明使得读出放大器能够在电源电压（例如，VCC）减小的环境中工作，并且不同的中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E， + EE VCC）最初建立在低于读出放大器正常灵敏度的电位。

    Semiconductor Memory Device And System Having Stacked Semiconductor Layers
    10.
    发明申请
    Semiconductor Memory Device And System Having Stacked Semiconductor Layers 审中-公开
    具有堆叠半导体层的半导体存储器件和系统

    公开(公告)号：US20110298011A1

    公开(公告)日：2011-12-08

    申请号：US13151691

    申请日：2011-06-02

    申请人： Sang-bo Lee ,  Kye-hyun Kyung

    发明人： Sang-bo Lee ,  Kye-hyun Kyung

    IPC分类号： H01L25/03

    CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L2224/0557 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05552

    摘要： Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software.

    摘要翻译： 示例性实施例涉及半导体存储器件和其中多个半导体层彼此堆叠的系统。 三维（3D）半导体存储器件可以包括堆叠在一起的多个半导体层。 多个半导体层可以具有相同的存储单元结构。 3D半导体存储器件可以包括包括用于存储系统数据的至少一个半导体层的第一存储器区域和包括用于存储除了系统数据之外的数据的至少一个半导体层的第二存储器区域。 系统数据可以包括从由引导代码，系统代码和应用软件组成的组中选择的至少一条数据。