公开(公告)号：US08666127B1

公开(公告)日：2014-03-04

申请号：US13204446

申请日：2011-08-05

Applicant: Young-Jae Kim ,  Byung-Jin Lee ,  Sang-Hoon Shin ,  Daniel Riley

Inventor： Young-Jae Kim ,  Byung-Jin Lee ,  Sang-Hoon Shin ,  Daniel Riley

IPC: G06K9/00

CPC classification number: G06K9/0012 ,  G06K9/033

Abstract: Methods and Apparatus are provided for fake fingerprint detection. In one embodiment, an apparatus for fake fingerprint detection includes a prism having a first side configured to be touched by a fingerprint, an IR LED located near the second side of the prism, a light source located near the third side of the prism, where both the IR LED and the light source are configured to illuminate the fingerprint simultaneously to produce a captured image of the fingerprint, one or more lenses configured to direct the captured image of the fingerprint for storage, one or more CMOS sensors configured to collect the captured image of the fingerprint for analysis, and a controller configured to determine validity of the fingerprint using the captured image.

Abstract translation: 提供了伪指纹检测的方法和装置。 在一个实施例中，一种用于假指纹检测的装置包括具有被指纹触摸的第一侧的棱镜，位于棱镜第二侧附近的IR LED，位于棱镜第三侧附近的光源， 红外LED和光源被配置为同时照亮指纹以产生指纹的捕获图像，一个或多个透镜被配置为将捕获的指纹图像引导存储，一个或多个CMOS传感器被配置为收集捕获的指纹 用于分析的指纹的图像，以及被配置为使用捕获的图像来确定指纹的有效性的控制器。

公开(公告)号：US08491489B2

公开(公告)日：2013-07-23

申请号：US11603015

申请日：2006-11-22

Applicant: Sang Hoon Shin ,  Sun Gi Hong ,  Kyung Ho Kim ,  Wan Taek Han

Inventor： Sang Hoon Shin ,  Sun Gi Hong ,  Kyung Ho Kim ,  Wan Taek Han

IPC: A61B5/08

CPC classification number: A61B5/08 ,  A61B5/0878 ,  A61B5/486 ,  A61B5/7405 ,  A61B5/742 ,  A61B7/003

Abstract: A system, medium, and method conducing a user's breathing, in which a sound generated during a user's exhale and/or an ambient temperature change occurring during the exhale is sensed to measure a respiratory waveform of the user. Respiratory information of the user may then be produced from the respiratory waveform, and when the respiratory information of the user is different from normal respiratory information of the user, breathing information according to the normal respiratory information may be provided to the user so the user can use the same to modify their breathing.

Abstract translation: 感测用户呼吸期间产生的声音和/或在呼出期间发生的环境温度变化的声音的系统，介质和方法，以测量用户的呼吸波形。 然后可以从呼吸波形产生用户的呼吸信息，并且当用户的呼吸信息不同于用户的正常呼吸信息时，可以向用户提供根据正常呼吸信息的呼吸信息，以便用户可以 使用相同的方式修改呼吸。

公开(公告)号：US20130094316A1

公开(公告)日：2013-04-18

申请号：US13340868

申请日：2011-12-30

Applicant: Sang Hoon SHIN ,  Hyung Dong LEE ,  Jeong Woo LEE ,  Young Suk MOON

Inventor： Sang Hoon SHIN ,  Hyung Dong LEE ,  Jeong Woo LEE ,  Young Suk MOON

IPC: G11C11/402

CPC classification number: G11C11/40603 ,  G11C11/40611 ,  G11C11/40615

Abstract: A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.

Abstract translation: 存储器系统包括：控制器，被配置为提供隐藏的自动刷新命令; 以及被配置为响应于所述隐藏的自动刷新命令执行刷新操作的存储器。 控制器和存储器彼此通信，使得控制器和存储器的每个刷新地址彼此具有相同的值。

公开(公告)号：US08300496B2

公开(公告)日：2012-10-30

申请号：US12948874

申请日：2010-11-18

Applicant: Tae Sik Yun ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

Inventor： Tae Sik Yun ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

IPC: G11C8/18 ,  G11C8/16 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C29/006 ,  G11C29/023

Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Abstract translation: 一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

公开(公告)号：US20120217654A1

公开(公告)日：2012-08-30

申请号：US13292609

申请日：2011-11-09

Applicant: Sang-Hoon SHIN ,  Kwan-Weon Kim

Inventor： Sang-Hoon SHIN ,  Kwan-Weon Kim

IPC: H01L27/10 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L22/20 ,  G11C5/04 ,  G11C29/08 ,  H01L21/561 ,  H01L22/14 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2224/81

Abstract: A semiconductor device includes a wafer comprising a chip that passes a test and a chip that does not pass a test, one or more first stacked chips that are stacked over the chip that passes a test, and one or more second stacked chips that are stacked over the chip that does not pass a test, wherein the second stacked chips comprise at least one between an chip that does not pass a test and a dummy chip.

Abstract translation: 半导体器件包括：晶片，其包括通过测试的芯片和不通过测试的芯片，堆叠在通过测试的芯片上的一个或多个第一堆叠芯片和堆叠的一个或多个第二堆叠芯片 在芯片上不通过测试，其中第二堆叠芯片包括不通过测试的芯片和虚设芯片之间的至少一个芯片。

公开(公告)号：US08237236B2

公开(公告)日：2012-08-07

申请号：US12762839

申请日：2010-04-19

Applicant: Jin Dong Song ,  Sung Jung Joo ,  Jin Ki Hong ,  Sang Hoon Shin ,  Kyung Ho Shin ,  Tae Yueb Kim ,  Ju Young Lim ,  Jin Seo Lee ,  Kung Won Rhie

Inventor： Jin Dong Song ,  Sung Jung Joo ,  Jin Ki Hong ,  Sang Hoon Shin ,  Kyung Ho Shin ,  Tae Yueb Kim ,  Ju Young Lim ,  Jin Seo Lee ,  Kung Won Rhie

IPC: H01L29/82

CPC classification number: H01L29/82

Abstract: An InSb-based switching device, which operates at room temperature by using a magnetic field controlled avalanche process for applying to magneto-logic elements, is provided. A switching device of one embodiment includes a p-type semiconductor layer; an n-type semiconductor layer; and contact layers disposed on one of the p-type and n-type semiconductor layers, the p-type semiconductor layer being in contact with the n-type semiconductor layer such that a current can be applied through the contact layers to the p-type and n-type semiconductor layers to cause a current flow from one of the contact layers to the p-type and n-type semiconductor layers and from the p-type and n-type semiconductor layers to the other of the contact layers, whereby the current flow can be controlled by an intensity of a magnetic field applied to the p-type and n-type semiconductor layers substantially perpendicularly thereto.

Abstract translation: 提供了一种基于InSb的开关装置，其通过使用用于应用于磁逻辑元件的磁场控制雪崩处理在室温下操作。 一个实施例的开关器件包括p型半导体层; n型半导体层; 以及设置在p型和n型半导体层中的一个上的接触层，p型半导体层与n型半导体层接触，使得可以通过接触层将电流施加到p型 和n型半导体层，以使电流从一个接触层流向p型和n型半导体层，并从p型和n型半导体层到另一个接触层，由此， 可以通过施加到基本垂直于其的p型和n型半导体层的磁场的强度来控制电流。

公开(公告)号：US20120155200A1

公开(公告)日：2012-06-21

申请号：US13299497

申请日：2011-11-18

Applicant: Young-Suk Moon ,  Hyung-Dong Lee ,  Jeong-Woo Lee ,  Sang-Hoon Shin

Inventor： Young-Suk Moon ,  Hyung-Dong Lee ,  Jeong-Woo Lee ,  Sang-Hoon Shin

IPC: G11C8/18 ,  G11C7/12 ,  G11C8/00

CPC classification number: G11C8/12 ,  G06F2213/0038

Abstract: A memory system includes a memory device, a control device configured to control the memory device, a first channel configured to transfer a row command from the control device to the memory device, and a second channel configured to transfer a column command from the control device to the memory device.

Abstract translation: 存储器系统包括存储器件，被配置为控制存储器件的控制器件，被配置为将控制器件的行命令传送到存储器件的第一通道以及被配置为从控制器件传送列命令的第二通道 到存储设备。

公开(公告)号：US20110186961A1

公开(公告)日：2011-08-04

申请号：US12836482

申请日：2010-07-14

Applicant: Young Hee YOON ,  Jun Gi Choi ,  Sang Hoon Shin

Inventor： Young Hee YOON ,  Jun Gi Choi ,  Sang Hoon Shin

IPC: H01L23/525

CPC classification number: H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.

Abstract translation: 提供了一种半导体集成电路。 半导体集成电路包括：一对互连; 连接该对互连的保险丝; 以及连接所述一对互连件的一个或多个散热图案，并且设置在保险丝周围。

公开(公告)号：US20110161581A1

公开(公告)日：2011-06-30

申请号：US12833066

申请日：2010-07-09

Applicant: Sang Hoon SHIN

Inventor： Sang Hoon SHIN

IPC: G06F13/28 ,  G11C8/04

CPC classification number: G11C8/18 ,  G11C7/1078

Abstract: A semiconductor circuit apparatus having a commonly shared control unit that coordinates reading and writing timed activities in two ranked subcircuits is presented. The semiconductor circuit includes: first and second ranks; and a rank control block shared by the first and second ranks and configured to provide a column-related command and an address to one of the first and second ranks in response to a chip select signal for selecting the first or second rank.

Abstract translation: 提出了具有共同共享的控制单元的半导体电路装置，其在两个排列的子电路中协调读写定时活动。 半导体电路包括：第一和第二等级; 以及由第一和第二等级共享的等级控制块，并且被配置为响应于用于选择第一或第二等级的片选信号，向第一和第二等级之一提供列相关命令和地址。

公开(公告)号：US20110024743A1

公开(公告)日：2011-02-03

申请号：US12648680

申请日：2009-12-29

Applicant: Jeong Woo LEE ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Hoon Shin ,  Xiang Hua Cui

Inventor： Jeong Woo LEE ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Hoon Shin ,  Xiang Hua Cui

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  G01R31/2884 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Abstract translation: 半导体集成电路包括具有多个半导体芯片的多芯片封装。 半导体集成电路包括信号线; 以及多个半导体芯片中的半导体芯片中的信号负载补偿部，被配置为响应于测试信号的激活而将设计的信号加载到信号线。 这里，设计的信号负载具有与信号线的多个半导体芯片中的另一半导体芯片的信号负载分量相对应的值。