公开(公告)号：US20160203044A1

公开(公告)日：2016-07-14

申请号：US14713140

申请日：2015-05-15

申请人： Sang-Hyuk KWON ,  Young-Hoon SON ,  Jung-Ho AHN

发明人： Sang-Hyuk KWON ,  Young-Hoon SON ,  Jung-Ho AHN

IPC分类号： G06F11/10 ,  H04L9/32 ,  G11C29/04

CPC分类号： G11C29/76 ,  G06F11/0766 ,  G06F11/1016 ,  G06F11/2094 ,  G06F12/0246 ,  G06F12/0802 ,  G06F17/3033 ,  G06F2212/1032 ,  G09C1/00 ,  G11C2029/4402 ,  H04L9/0643 ,  H04L2209/12

摘要： A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.

摘要翻译： 存储器件可以包括存储单元阵列，开关滤波器电路，高速缓冲存储器电路和选择电路。 布鲁斯滤波电路可以被配置为输出指示接收到的地址是与存储器单元阵列的故障单元相对应的失败地址之一的可能性的确定结果信号。 高速缓冲存储器电路可以被配置为存储失败的地址和对应于各个故障地址的第一组数据，并且被配置为当确定结果信号指示可能时，通过确定接收到的地址是否一致来提供比较结果信号 其中一个失败的地址。 选择电路可以被配置为基于确定结果信号和比较结果信号输出与接收到的地址相对应的第一组数据或第二数据的第一数据或存储单元阵列的第二数据。

公开(公告)号：US20130094320A1

公开(公告)日：2013-04-18

申请号：US13610995

申请日：2012-09-12

申请人： Jae-Ki YOO ,  Sang-Hyuk Kwon ,  Sang-Woong Shin ,  In-Chul Jeong

发明人： Jae-Ki YOO ,  Sang-Hyuk Kwon ,  Sang-Woong Shin ,  In-Chul Jeong

IPC分类号： G11C8/10 ,  G11C8/00

CPC分类号： G11C8/06 ,  G06F12/02 ,  G06F12/1408

摘要： Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address.

摘要翻译： 提供地址转换方法。 所述方法可以包括当半导体存储器件加电时产生上电信号。 所述方法还可以包括响应于上电信号产生随机输出信号。 所述方法可以另外包括响应于随机输出信号变换第一地址的位以产生第二地址。

公开(公告)号：US20130068368A1

公开(公告)日：2013-03-21

申请号：US13592679

申请日：2012-08-23

申请人： Sung-Kook KIM ,  Kyoung-Ho Yang ,  Jin-Ho Choi ,  Sang-Hyuk Kwon ,  Yong-Shin Cho

发明人： Sung-Kook KIM ,  Kyoung-Ho Yang ,  Jin-Ho Choi ,  Sang-Hyuk Kwon ,  Yong-Shin Cho

IPC分类号： G01N21/01 ,  H05B33/10 ,  G01B11/26

CPC分类号： G01R31/2635 ,  G01R31/2893 ,  G09G3/006 ,  H01L51/0031

摘要： A testing apparatus for testing an organic light-emitting display apparatus including: a test chamber for retaining a first substrate having a plurality of exposed cells, each cell including an organic emission unit; a stage in the test chamber, the stage configured to support the first substrate; a plurality of probe bars, each of the probe bars including a plurality of probe blocks for respectively contacting the exposed plurality of cells of the first substrate to supply an external signal to the exposed plurality of cells; a probe bar moving unit coupled to the probe bar; and a probe bar supply unit including the plurality of probe bars, wherein the probe bar moving unit is configured to move a probe bar to and from the stage and to and from the supply unit to obtain and unload a probe bar.

摘要翻译： 一种用于测试有机发光显示装置的测试装置，包括：用于保持具有多个曝光单元的第一基板的测试室，每个单元包括有机发射单元; 在所述测试室中的阶段，所述阶段被配置为支撑所述第一基板; 多个探针杆，每个探针棒包括多个探针块，用于分别接触暴露的第一衬底的多个单元以向暴露的多个单元提供外部信号; 耦合到探针杆的探针杆移动单元; 以及包括所述多个探针棒的探针杆供给单元，其中所述探针杆移动单元被配置为将探针杆移动到所述载物台和从所述载物台移动到所述供应单元并从所述供应单元移动并获取和卸载探针杆。

公开(公告)号：US20110235441A1

公开(公告)日：2011-09-29

申请号：US13067404

申请日：2011-05-31

申请人： Sang-hyuk Kwon ,  Hi-choon Lee

发明人： Sang-hyuk Kwon ,  Hi-choon Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074

摘要： A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

公开(公告)号：US20100244915A1

公开(公告)日：2010-09-30

申请号：US12659881

申请日：2010-03-24

申请人： Sang-Hyuk Kwon ,  Byung Hoon Jeong ,  Jae Woong Lee

发明人： Sang-Hyuk Kwon ,  Byung Hoon Jeong ,  Jae Woong Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0802

摘要： In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.

摘要翻译： 在示例性实施例中，半导体器件包括时钟信号产生电路。 时钟信号生成电路被配置为响应于外部时钟信号和读取命令信号而生成至少一个控制时钟信号。 时钟信号生成电路包括多个延迟电路，并且时钟信号生成电路被配置为选择性地禁用多个延迟电路中的至少一个以减少功耗。

公开(公告)号：US20100128543A1

公开(公告)日：2010-05-27

申请号：US12697547

申请日：2010-02-01

申请人： Sang-hyuk KWON ,  Byung-hoon JEONG

发明人： Sang-hyuk KWON ,  Byung-hoon JEONG

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

摘要翻译： 用于半导体存储器件的等待时间电路包括等待时间控制时钟发生器，其产生来自外部时钟的m分割除法信号和来自m分割除法信号的至少一个等待时间控制时钟，其中m是大于 等待时间电路还包括响应于至少一个等待时间控制时钟产生等待时间信号的等待时间信号发生器，等待时间控制信号和内部读取命令信号，其中等待时间控制信号是从列产生的 地址选通（CAS）延迟和内部读命令信号是响应于接收到的读命令产生的。

公开(公告)号：US20060120588A1

公开(公告)日：2006-06-08

申请号：US11272479

申请日：2005-11-10

申请人： Sang-Hyuk Kwon ,  Kyoung-Ho Yang ,  Soon-Jae Park

发明人： Sang-Hyuk Kwon ,  Kyoung-Ho Yang ,  Soon-Jae Park

IPC分类号： G06K9/00

CPC分类号： G09G3/006

摘要： A test system includes a rotatable turntable, a loading section, a first image pickup section, a second image pickup section, a system control section and an unloading section. The loading section loads a display panel assembly onto the stage. The loading section recognizes a unique number of the display panel assembly. The first image pickup section obtains an active area image data from an active area image. A valid first active area defect is detected using an active area image data obtained from an active area image displayed on the display panel assembly. An inactive area defect is detected based on an inactive area image data and a reference inactive area image data.

摘要翻译： 测试系统包括可旋转转盘，装载部分，第一图像拾取部分，第二图像拾取部分，系统控制部分和卸载部分。 装载部分将显示面板组件装载到舞台上。 加载部分识别显示面板组件的唯一编号。 第一图像拾取部分从活动区域图像获得有效区域图像数据。 使用从显示面板组件上显示的活动区域图像获得的有效区域图像数据来检测有效的第一有效区域缺陷。 基于非活动区域图像数据和参考无效区域图像数据来检测非活动区域缺陷。

公开(公告)号：US08045406B2

公开(公告)日：2011-10-25

申请号：US12697547

申请日：2010-02-01

申请人： Sang-hyuk Kwon ,  Byung-hoon Jeong

发明人： Sang-hyuk Kwon ,  Byung-hoon Jeong

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

摘要翻译： 用于半导体存储器件的等待时间电路包括等待时间控制时钟发生器，其产生来自外部时钟的m分割除法信号和来自m分割除法信号的至少一个等待时间控制时钟，其中m是大于 等待时间电路还包括响应于至少一个等待时间控制时钟产生等待时间信号的等待时间信号发生器，等待时间控制信号和内部读取命令信号，其中等待时间控制信号是从列产生的 地址选通（CAS）延迟和内部读命令信号是响应于接收到的读命令产生的。

公开(公告)号：US08339870B2

公开(公告)日：2012-12-25

申请号：US13067404

申请日：2011-05-31

申请人： Sang-hyuk Kwon ,  Hi-choon Lee

发明人： Sang-hyuk Kwon ,  Hi-choon Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074

摘要： A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

摘要翻译： 高压发生电路可以包括脉冲信号发生器，计数器，多个发射器和/或多个泵器。 脉冲信号发生器可以被配置为响应于刷新命令信号被使能以输出脉冲信号。 计数器可以被配置为对脉冲信号进行计数并顺序地输出多个选择信号。 多个发射机可以被配置为响应于多个选择信号的各个选择信号而被顺序启用以发送脉冲信号。 多个泵器可以对应于多个发射器。 多个泵器中的每一个可以被配置为基于来自多个发射器的相应发射器的所发射的脉冲信号共同地产生高电压。

公开(公告)号：US08294499B2

公开(公告)日：2012-10-23

申请号：US12659881

申请日：2010-03-24

申请人： Sang-Hyuk Kwon ,  Byung Hoon Jeong ,  Jae Woong Lee

发明人： Sang-Hyuk Kwon ,  Byung Hoon Jeong ,  Jae Woong Lee

IPC分类号： H03K3/84

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0802

摘要： In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.

摘要翻译： 在示例性实施例中，半导体器件包括时钟信号产生电路。 时钟信号生成电路被配置为响应于外部时钟信号和读取命令信号而生成至少一个控制时钟信号。 时钟信号生成电路包括多个延迟电路，并且时钟信号生成电路被配置为选择性地禁用多个延迟电路中的至少一个以减少功耗。