公开(公告)号：US07261982B2

公开(公告)日：2007-08-28

申请号：US10736295

申请日：2003-12-15

申请人： Barthelemy Fondeur ,  Anca L. Sala ,  Robert J. Brainard ,  David K. Nakamoto ,  Tom Truong ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan

发明人： Barthelemy Fondeur ,  Anca L. Sala ,  Robert J. Brainard ,  David K. Nakamoto ,  Tom Truong ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan

IPC分类号： G03F1/00 ,  G03C5/00

CPC分类号： G03F7/70466 ,  G03F1/50 ,  G03F1/70

摘要： The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.

摘要翻译： 本申请涉及使用光刻掩模组，光刻掩模组以及用光刻掩模组制造的平面电路制造平面电路的方法。 本发明涉及将光刻掩模分为两部分，即主掩模和一个或多个从属掩模。 主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。 特别地，主掩模用作模板以提供用于平面电路的总体布局，而每个从屏蔽被改变以调谐和/或定制平面电路。 由于只有一小部分平面电路被重新设计和/或重写为新的掩模（即，从属掩模），本发明提供了一种用于优化平面电路的简单且成本有效的方法。 此外，由于大多数掩模错误将源自主掩模，本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。

公开(公告)号：US06947653B2

公开(公告)日：2005-09-20

申请号：US09977065

申请日：2001-10-12

申请人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  Niranjan Gopinathan ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

发明人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  Niranjan Gopinathan ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

IPC分类号： G02B6/12 ,  G02B6/13 ,  G02B6/136 ,  G02B6/34 ,  G02B6/10 ,  G02F1/295

CPC分类号： G02B6/1203 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/12097 ,  G02B2006/12176

摘要： A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.

摘要翻译： 平面光波电路包括至少一个光波导芯，并且靠近芯的至少一个特征具有应力工程化特性以平衡应力，从而最小化影响芯的双折射。 在芯上形成保护性钝化层，并且该特征基本上不受由特征提供的平衡应力的干扰。 应力平衡特征可以是在芯上形成的外包层，被掺杂以具有与下层衬底的热膨胀系数近似匹配的热膨胀系数，以便在外包层和衬底之间的下包层对称地分布应力。 保护钝化层形成为具有与外包层大致匹配的热膨胀系数。 在一个示例性实施例中，钝化层由氮化硅形成。 还公开了应力释放槽和芯过蚀刻的相关概念。

公开(公告)号：US06905616B2

公开(公告)日：2005-06-14

申请号：US10382562

申请日：2003-03-05

申请人： Ajay Kumar ,  Anisul H Khan ,  Sanjay M Thekdi ,  Sharma V Pamarthy

发明人： Ajay Kumar ,  Anisul H Khan ,  Sanjay M Thekdi ,  Sharma V Pamarthy

IPC分类号： B31D3/00 ,  B44C1/22 ,  B81C1/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/00

CPC分类号： B81C1/00952

摘要： Micro devices are formed in situ in a high density in a substrate comprising a masked silicon layer over a stop layer of a silicon compound, by anisotropically etching the desired feature in the silicon layer, overetching to form a notch at the silicon-stop layer interface, depositing a protective fluorocarbon polymer layer on the sidewalls and bottom of the etched silicon layer, and isotropically etching to separate the etched feature from the stop layer. This method avoids the problems of stiction common in other methods of forming micro devices.

摘要翻译： 通过各向异性地蚀刻硅层中的所需特征，在基底上形成微孔器件，在衬底上形成掩模硅层，通过各向异性蚀刻硅层中的所需特征，过蚀刻以在硅 - 停止层界面处形成缺口 ，在蚀刻硅层的侧壁和底部上沉积保护性碳氟聚合物层，并进行各向同性蚀刻以将蚀刻的特征与停止层分离。 这种方法避免了在其他形成微器件的方法中常见的静电问题。

公开(公告)号：US06697553B2

公开(公告)日：2004-02-24

申请号：US10077581

申请日：2002-02-15

申请人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

发明人： Jyoti Kiron Bhardwaj ,  Robert James Brainard ,  David J. Chapman ,  Douglas E. Crafts ,  Zi-Wen Dong ,  David Dougherty ,  Erik W. Egan ,  James F. Farrell ,  Mark B. Farrelly ,  Niranjan Gopinathan ,  Kenzo Ishida ,  David K. Nakamoto ,  Thomas Thuan Nguyen ,  Suresh Ramalingam ,  Steven M. Swain ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan ,  Hiroaki Yamada ,  Yingchao Yan

IPC分类号： G02B634

CPC分类号： G02B6/12011 ,  G02B6/105 ,  G02B6/12 ,  G02B6/12016 ,  G02B6/12021 ,  G02B6/12026

摘要： A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

摘要翻译： 平面光波电路包括阵列波导光栅（AWG），其具有输入和输出波导，具有相应长度差的部分弯曲阵列波导和用于在输入/输出和阵列波导之间聚焦光能的平面波导区域。 公开了沿着平面波导区域面的最佳波导宽度和间距，其主要决定于AWG尺寸和光学性能。 还公开了最佳横截面波导尺寸（例如，宽度和高度）; 波导芯和包层区之间的折射率差异; 和最佳阵列波导长度，路径长度差和自由光谱范围。 这些特性，特别是结合先进的光纤附着，钝化和封装技术，可以获得高产出，高性能的AWG（高斯型和平板型）。

公开(公告)号：US07162108B2

公开(公告)日：2007-01-09

申请号：US11015223

申请日：2004-12-17

申请人： Anca L. Sala ,  Duncan W. Harwood ,  Barthelemy Fondeur ,  Anantharaman Vaidyanathan ,  Robert J. Brainard ,  Sanjay M. Thekdi ,  Thomas T. Nguyen ,  Ian Hutagalung

发明人： Anca L. Sala ,  Duncan W. Harwood ,  Barthelemy Fondeur ,  Anantharaman Vaidyanathan ,  Robert J. Brainard ,  Sanjay M. Thekdi ,  Thomas T. Nguyen ,  Ian Hutagalung

IPC分类号： G02F1/01 ,  G02F1/035 ,  G02F1/00 ,  G02B26/00 ,  G02B6/26 ,  G02B6/42

CPC分类号： G02F1/0147 ,  G02B6/12007 ,  G02B6/266 ,  G02F1/21 ,  G02F2001/0113 ,  G02F2001/212 ,  G02F2203/06

摘要： The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all. Segmented trenches appear to allow for the lowest stress on the two waveguide arms of all the cases including no trench and trenched devices.

摘要翻译： 本发明涉及一种构成马赫曾德平面光波回路的可变光衰减器，特别是包括用于隔热和应力释放的通道波导支撑结构，以减少器件中的偏振相关损耗（PDL）和功耗。 功率减小沟槽包括在蚀刻工艺中在它们之间具有小的应力消除柱的包层材料的纵向段。 MZI的波导由主柱结构和消除沟槽后保留的积分应力消除柱支撑。 波导三面被空气包围，以改善热隔离。 与现有技术的连续沟槽设计相比，本发明的性能显示出PDL和消光比的显着改善，并且在更少的程度上，在完全不使用功率降低沟槽的情况下。 分段沟槽似乎允许在所有情况下的两个波导臂上的最小应力，包括没有沟槽和沟槽的器件。