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    Method and structure for optimizing yield of 3-D chip manufacture
    6.
    发明授权
    Method and structure for optimizing yield of 3-D chip manufacture 有权
    优化3-D芯片制造产量的方法和结构

    公开(公告)号：US07999377B2

    公开(公告)日：2011-08-16

    申请号：US12029122

    申请日：2008-02-11

    申请人： Edward M. DeMulder ,  Sarah H. Knickerbocker ,  Michael J. Shapiro ,  Albert M. Young

    发明人： Edward M. DeMulder ,  Sarah H. Knickerbocker ,  Michael J. Shapiro ,  Albert M. Young

    IPC分类号： H01L23/488

    CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L2224/13

    摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

    摘要翻译： 该过程开始于具有互补芯片的单独的器件晶片。 薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。 处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。 捕获垫被去除并在变薄后更换。 切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。 具有已知良好3-D芯片的器件晶片然后进行最终处理。

    PROCESS FOR MAKING INTERCONNECT SOLDER Pb-FREE BUMPS FREE FROM ORGANO-TIN/TIN DEPOSITS ON THE WAFER SURFACE
    8.
    发明申请
    PROCESS FOR MAKING INTERCONNECT SOLDER Pb-FREE BUMPS FREE FROM ORGANO-TIN/TIN DEPOSITS ON THE WAFER SURFACE 有权
    制造互连焊接工艺的方法无铅焊锡从无机表面上的有机锡/锡沉积物

    公开(公告)号：US20090020590A1

    公开(公告)日：2009-01-22

    申请号：US11778678

    申请日：2007-07-17

    申请人： Sarah H. Knickerbocker ,  Sean A. Allen ,  John J. Garant ,  Jerry A. Gorrell ,  Phillip W Palmatier ,  Christopher L. Tessler

    发明人： Sarah H. Knickerbocker ,  Sean A. Allen ,  John J. Garant ,  Jerry A. Gorrell ,  Phillip W Palmatier ,  Christopher L. Tessler

    IPC分类号： B23K31/02

    CPC分类号： B23K3/0623 ,  B23K2101/40

    摘要： A method is provided for making of interconnect solder bumps on a wafer or other electronic device without depositing any significant amount of tin or other solder component from the solder onto the wafer surface which tin can cause shorts or other defects in the wafer. The method is particularly useful for well-known C4NP interconnect technology. In one aspect of the invention, a reducing gas flow rate is used to remove oxides from the solder surfaces and wafer pad surfaces and is of a sufficient determined or pre-determined flow and/or chamber or mold/wafer spacing to provide a gas velocity across the solder surfaces and wafer pad surfaces so that Sn or other contaminants do not deposit on the wafer surface during solder transfer. In another aspect, the transfer contact is performed below the melting point of the solder and subsequently heated to above the melting temperature while in transfer contact. The heated solder in contact with the wafer pads is transferred to the wafer pads.

    摘要翻译： 提供了一种用于在晶片或其他电子器件上制造互连焊料凸块的方法，而不会将任何显着量的锡或其他焊料组分从焊料沉积到晶片表面上，锡可能导致晶片中的短路或其它缺陷。 该方法对于众所周知的C4NP互连技术特别有用。 在本发明的一个方面，使用还原气体流速从焊料表面和晶片焊盘表面去除氧化物，并且具有足够的确定或预定的流动和/或室或模具/晶片间距以提供气体速度 穿过焊料表面和晶片焊盘表面，使得Sn或其他污染物在焊料传输期间不会沉积在晶片表面上。 在另一方面，转移接触在焊料的熔点之下进行，随后在转移接触的同时被加热至高于熔融温度。 与晶片焊盘接触的加热焊料被转移到晶片焊盘。

    Method and Structure for Optimizing Yield of 3-D Chip Manufacture
    9.
    发明申请
    Method and Structure for Optimizing Yield of 3-D Chip Manufacture 有权
    优化3-D芯片制造产量的方法和结构

    公开(公告)号：US20080142959A1

    公开(公告)日：2008-06-19

    申请号：US12029122

    申请日：2008-02-11

    申请人： Edward M. DeMulder ,  Sarah H. Knickerbocker ,  Michael J. Shapiro ,  Albert M. Young

    发明人： Edward M. DeMulder ,  Sarah H. Knickerbocker ,  Michael J. Shapiro ,  Albert M. Young

    IPC分类号： H01L23/488

    CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L2224/13

    摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

    摘要翻译： 该过程开始于具有互补芯片的单独的器件晶片。 薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。 处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。 捕获垫被去除并在变薄后更换。 切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。 具有已知良好3-D芯片的器件晶片然后进行最终处理。