公开(公告)号：US08901741B2

公开(公告)日：2014-12-02

申请号：US13531518

申请日：2012-06-23

申请人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L23/522 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US20110210449A1

公开(公告)日：2011-09-01

申请号：US13089958

申请日：2011-04-19

申请人： SATYA V. NITTA ,  Shom Ponoth

发明人： SATYA V. NITTA ,  Shom Ponoth

IPC分类号： H01L23/48

CPC分类号： H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

摘要翻译： 双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。 沟槽和导电金属柱和通孔具有共同的轴线。 这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。 在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及 在通孔中向下延伸距离线下方约1埃至通孔的整个深度。 在另一方面，制品包括封盖的双镶嵌结构。

公开(公告)号：US20110210448A1

公开(公告)日：2011-09-01

申请号：US13083550

申请日：2011-04-09

申请人： Satya V. Nitta ,  Shom Ponoth

发明人： Satya V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/48 ,  B82Y99/00

CPC分类号： H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

摘要翻译： 双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。 沟槽和导电金属柱和通孔具有共同的轴线。 这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。 在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及 在通孔中向下延伸距离线下方约1埃至通孔的整个深度。 在另一方面，制品包括封盖的双镶嵌结构。

公开(公告)号：US20110121457A1

公开(公告)日：2011-05-26

申请号：US13021774

申请日：2011-02-06

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

IPC分类号： H01L23/532 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/7682

摘要： A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

摘要翻译： 在具有电介质层的基板上产生气隙的方法包括通过需要气隙的光刻来定义线。 线的尺寸通过修整工艺（各向同性蚀刻）收缩。 图案的色调通过施加被向下蚀刻到图案的顶部的平坦化层来反转。 去除光致抗蚀剂，导致亚光刻沟槽，其转移到盖层中，最终转移到两条金属线之间的电介质中。 暴露的电介质最终被损坏，并被蚀刻掉，导致金属线之间的气隙。 间隙通过在随后的电介质的沉积期间发生的夹断来密封。

公开(公告)号：US07939446B1

公开(公告)日：2011-05-10

申请号：US12616259

申请日：2009-11-11

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

IPC分类号： H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/7682

摘要： A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

摘要翻译： 在具有电介质层的基板上产生气隙的方法包括通过需要气隙的光刻来定义线。 线的尺寸通过修整工艺（各向同性蚀刻）收缩。 图案的色调通过施加被向下蚀刻到图案的顶部的平坦化层来反转。 去除光致抗蚀剂，导致亚光刻沟槽，其转移到盖层中，最终转移到两条金属线之间的电介质中。 暴露的电介质最终被损坏，并被蚀刻掉，导致金属线之间的气隙。 间隙通过在随后的电介质的沉积期间发生的夹断来密封。

公开(公告)号：US20090075472A1

公开(公告)日：2009-03-19

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US07361991B2

公开(公告)日：2008-04-22

申请号：US10666564

申请日：2003-09-19

申请人： Katherine L Saenger ,  Maheswaran Surendra ,  Anna Dorothy Karecki, legal representative ,  Satya V Nitta ,  Sampath Purushothaman ,  Matthew E Colburn ,  Timothy J Dalton ,  Elbert Huang

发明人： Simon M Karecki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectric and the optional interconnect vias located underneath. The lines and the lateral gap between them are straddled on top by a cap layer so that a closed air gap is formed. Several embodiments of this structure and methods to fabricate the same are also described.

摘要翻译： 描述了封闭气隙互连结构。 该结构包括在互连线下方的永久支撑电介质的离散区域，使得除了支撑电介质的离散区域和位于下方的可选互连通孔之外，线路基本上被空气包围。 它们之间的线和横向间隙由顶盖跨在顶部，从而形成封闭的气隙。 还描述了这种结构的几个实施例及其制造方法。

公开(公告)号：US08481423B2

公开(公告)日：2013-07-09

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

公开(公告)号：US20110020753A1

公开(公告)日：2011-01-27

申请号：US12510001

申请日：2009-07-27

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

IPC分类号： G03F7/20

CPC分类号： G03F7/091 ,  G03F7/40 ,  H01L21/3086

摘要： A method for reversing the tone of a lithographic image on a substrate comprises depositing a modifiable material on a substrate; applying a photolithographic material on the modifiable material: defining a removable patterned area in the photolithopgraphic material by photolithograpic means; removing the patterned area to produce an exposed region in the modifiable material that substantially conforms to the patterned area; producing a reacted modifiable material by increasing the etch resistance of the modifable material substantially throughout the exposed region so that the etch resistance of the exposed region comprises a region that substantially conforms to the exposed region; and removing the photoresist and the modifiable material to leave the reacted modifiable material and substrate.

摘要翻译： 用于反转基底上的平版印刷图像的色调的方法包括将可修改材料沉积在基底上; 将光刻材料施加在可修改的材料上：通过光刻手段在光致剪切材料中限定可移除的图案区域; 去除所述图案化区域以在所述可修改材料中产生基本上符合所述图案化区域的暴露区域; 通过增加可修饰材料的基本上在整个曝光区域的耐蚀刻性而产生可反应的可修饰材料，使得暴露区域的耐蚀刻性包括基本上符合曝光区域的区域; 并除去光致抗蚀剂和可修改的材料以留下可反应的可修改的材料和基材。

公开(公告)号：US20090298281A1

公开(公告)日：2009-12-03

申请号：US12539488

申请日：2009-08-11

申请人： Chih-Chao Yang ,  Satya V. Nitta

发明人： Chih-Chao Yang ,  Satya V. Nitta

IPC分类号： H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material.

摘要翻译： 提供了互连结构，其中导电特征（即，导电材料）不与电介质材料的上表面共面，而是导电材料凹陷在电介质材料的上表面下方。 除了凹陷在介电材料的上表面之外，互连结构的导电材料通过扩散阻挡材料在所有侧面（即，侧壁表面，上表面和底表面）上被包围。 与现有技术的互连结构不同，位于凹陷导电材料的上表面上的阻挡材料定位成具有包括凹入的导电材料的开口。