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1.发明授权Method for manufacturing a structure in a semiconductor device and a structure in a semiconductor device 有权半导体装置的结构的制造方法以及半导体装置的结构公开(公告)号：US07767571B2
公开(公告)日：2010-08-03
申请号：US11549487
申请日：2006-10-13
IPC分类号： H01L21/84
CPC分类号： H01L21/76838 , H01L23/525 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The invention is concerned with a method for manufacturing a local wiring in a semiconductor device, comprising the manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step.
摘要翻译： 本发明涉及一种用于制造半导体器件中的局部布线的方法，包括在衬底上的分层叠层中制造基本上处于相同水平位置的至少两个导电结构，所述至少两个导电结构被分离 通过填充有至少一种介电材料的间隙，所述间隙由导电材料电桥接，以形成至少一个电连接所述至少两个导电结构的接触元件，由此在单个光刻步骤中产生至少一个接触元件 。
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2.发明申请Transistor arrangement, sense-amplifier arrangement and methods of manufacturing the same via a phase shift mask 审中-公开晶体管布置，读出放大器布置以及通过相移掩模制造它们的方法公开(公告)号：US20080042171A1
公开(公告)日：2008-02-21
申请号：US11506205
申请日：2006-08-18
申请人： Sebastian Mosler , Mario Hennig , Karsten Zeiler , Thi Phuong Hoa Nguyen , Rainer Pforr , Jorg Thiele
发明人： Sebastian Mosler , Mario Hennig , Karsten Zeiler , Thi Phuong Hoa Nguyen , Rainer Pforr , Jorg Thiele
IPC分类号： H01L29/76 , H01L21/8234 , H01L27/108 , H01L21/8242
CPC分类号： H01L27/088 , G03F1/30 , H01L27/0207 , H01L27/10885
摘要： Methods of forming transistor arrangements using alternating phase shift masks are provided. The mask may include two parallel opaque lines, a first transparent section separating the opaque lines and a second transparent section in the rest. The second transparent section may shift the phase with respect to the first transparent section by 180 degree. A phase conflict occurs along an edge between the first and the second transparent sections. A semiconductor substrate is patterned via the mask and, from the opaque lines functional active areas of a transistor pair and from the phase conflict edge, thereby resulting in a parasitic area. A separation gate is provided that is capable of switching off a parasitic transistor being formed within the parasitic area. Channel widths may be stabilized and maximized within dense transistor arrangements, for example, in a multiplexer portion of a sense amplifier arrangement for memory cell arrays.
摘要翻译： 提供了使用交替相移掩模形成晶体管布置的方法。 掩模可以包括两个平行的不透明线，分隔不透明线的第一透明部分和其余部分中的第二透明部分。 第二透明部分可以将相位相对于第一透明部分移位180度。 沿着第一和第二透明部分之间的边缘发生相位冲突。 通过掩模对半导体衬底进行图案化，并且从不透明线将晶体管对的功能有效区域和相冲突边缘图案化，由此导致寄生区域。 提供了一种能够关闭在寄生区域内形成的寄生晶体管的分离栅极。 通道宽度可以在致密晶体管布置中稳定和最大化，例如在用于存储单元阵列的读出放大器装置的多路复用器部分中。
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3.发明申请Method for Manufacturing a Structure in a Semiconductor Device and a Structure in a Semiconductor Device 有权半导体装置的结构的制造方法以及半导体装置的结构公开(公告)号：US20080090398A1
公开(公告)日：2008-04-17
申请号：US11549487
申请日：2006-10-13
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L23/525 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The invention is concerned with a method for manufacturing a local wiring in a semiconductor device, comprising the manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step.
摘要翻译： 本发明涉及一种用于制造半导体器件中的局部布线的方法，包括在衬底上的分层叠层中制造基本上处于相同水平位置的至少两个导电结构，所述至少两个导电结构被分离 通过填充有至少一种介电材料的间隙，所述间隙由导电材料电桥接，以形成至少一个电连接所述至少两个导电结构的接触元件，由此在单个光刻步骤中产生至少一个接触元件 。
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4.发明授权Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement 有权共同位于半导体器件的阱中的多个电阻器的布置以及包括至少一个这样的布置的半导体器件公开(公告)号：US07049930B2
公开(公告)日：2006-05-23
申请号：US10663354
申请日：2003-09-16
IPC分类号： H01C1/01
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/0802 , H01L27/10897 , H01L27/118
摘要： An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at least one such arrangement of resistors, wherein the resistors, when viewed in a longitudinal direction of the resistors, are displaced in relation to one another.
摘要翻译： 共同位于半导体器件的同一个阱中的多个电阻器的布置以及包括至少一个这样的电阻器布置的半导体器件，其中当沿电阻器的纵向方向观察时，电阻器被移位 相互之间。
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